Data Sheet

Flash Map—Ethernet Controller I210
203
6.2.26 PCIe Control 3 (Word 0x29)
This word is used for programming PCIe functionality and function disable control.
1
At most one of these two bits may be set.
6.2.27 End of Read-Only (RO) Area (Word 0x2C)
Defines the end of the area in the Flash that is RO. This is a Read Only (RO) value.
6.2.28 Start of RO Area (Word 0x2D)
Defines the start of the area in the Flash that is RO. This is a Read Only (RO) value.
Bits Name
Default HW
Mode
Description
15 en_pin_pcie_func_dis 0b
When set to 1b, enables disabling the PCIe function by driving the SDP_1 pin to
0b (refer to Section 4.4.3).
Note: The SDP_1 pin on the port is sampled on power up and during PCIe reset.
14 Reserved 0b Reserved.
13
nvm_alt_aux_pwr_en
1
0b
When set to 1b, SDP_3 pad controls the auxiliary power functionality. When
SDP_3 pad is driven high, it indicates that auxiliary power is provided.
12 Reserved 0b Reserved.
11 Reserved 0b Reserved.
10 nvm_aux_pwr_en
1
0b
When set to 1b, DEV_OFF_N pad controls the auxiliary power functionality. When
DEV_OFF_N pad is driven high, it indicates that auxiliary power is provided.
9:7 Reserved 0x0 Reserved
6 Reserved 0b Reserved
5 Wake_pin_enable 0b
Enables the use of the WAKE# pin for a PME event in all non-LTSSM L2 power
states. When bit is set to 1b, the WAKE# pin is asserted even when the device is
not in D3cold state, if a wake event is detected.
4:0 Reserved 11100b
Reserved.
In NVM/iNVM, set this field like its HW default value.
Bit Name Description
15:11 Reserved Reserved.
10:0 EORO_area (RO)
Defines the end of the area in the Flash that is RO. The resolution is one word and can be up to byte
address 0x7FF. A value of zero indicates no RO area.
Bit Name Description
15:11 Reserved Reserved.
10:0 SORO_area (RO)
Defines the start of the area in the Flash that is RO. The resolution is one word and can be up to
word address 0x7FF.