Data Sheet

Ethernet Controller I210 —Flash Map
202
6.2.25 PCIe Control 2 (Word 0x28)
This word is used to configure the initial settings for the PCIe default functionality.
5:4 Link Mode 00b
Initial value of Link Mode bits of the Extended Device Control
(CTRL_EXT.LINK_MODE) register, specifying which link interface and protocol is
used by the MAC.
00b = MAC operates with internal copper PHY (10/100/1000BASE-T).
01b = MAC and SerDes I/F operate in 1000BASE-KX mode.
10b = MAC and SerDes operate in SGMII mode.
11b = MAC and SerDes I/F operate in SerDes (1000BASE-BX) mode.
See Section 8.2.3.
3 Reserved 0b Reserved.
2External MDIO0b
When set, the PHY management interface is via the external MDIO interface. Loaded
to MDICNFG.Destination (refer to Section 8.2.5).
1EXT_VLAN 0b
Sets the default for CTRL_EXT[26] bit. Indicates that additional VLAN is expected in
this system (refer to Section 8.2.3).
0
Keep_PHY_Link_U
p_En
0b
Enables No PHY Reset when the MC indicates that the PHY should be kept on. When
asserted, this bit prevents the PHY reset signal and the power changes reflected to
the PHY according to the MANC.Keep_PHY_Link_Up value.
Bits Name
Default HW
Mode
Description
15:14 Reserved Reserved
13
ECRC Generation for
MCTP
0b
0b = Add ECRC to MCTP packets if ECRC is enabled via the ECRC Generation
Enable field in PCIe Advanced Error Capabilities and Control register.
1b = Do not add ECRC to MCTP packets even if ECRC is enabled.
Should be cleared in normal operation.
12 ECRC Check 1b
Loaded into the ECRC Check Capable bit of the PCIe Advanced Error Capabilities
and Control register.
0b = Function is not capable of checking ECRC.
1b = Function is capable of checking ECRC.
11 ECRC Generation 1b
Loaded into the ECRC Generation Capable bit of the PCIe Advanced Error
Capabilities and Control register.
0b = Function is not capable of generating ECRC.
1b = Function is capable of generating ECRC.
10 FLR Capability Enable 1b
FLR Capability Enable bit is loaded to the PCIe configuration registers -> Device
Capabilities.
9:6 FLR Delay 0x1
Delay in microseconds from D0 to D3 move until a reset assertion.
Meaningless when the FLR delay disable bit is set to 1b.
5 FLR Delay Disable 1b
FLR Delay Disable
0 = Add delay to FLR assertion.
1 = Do not add delay to FLR assertion.
4 Reserved Reserved.
3:1 FLBAR_Size 111b
Indicates the Flash size to be exposed in the host memory BAR according to the
following equation:
Size = 64 KB * 2**(FLBAR_Size field). From 0.5 MB up to 8 MB in powers of 2.
This impacts the requested memory space for the Flash and Expansion ROM BARs
in PCIe configuration space.
Note:
When CSR_Size and FLBAR_Size fields in the Flash are set to 0x0, Flash
BAR in the PCI configuration space is disabled.
0CSR_Size 0b
The CSR_Size and FLBAR_Size fields define the usable Flash size and CSR
mapping window size as shown in BARCTRL register description.
Note: When CSR_Size and FLBAR_size fields in the Flash are set to 0b, Flash BAR
in the PCI configuration space is disabled.
Bit Name
Default HW
Mode
Description