Data Sheet

Flash Map—Ethernet Controller I210
201
6.2.23 LAN Power Consumption (Word 0x22)
6.2.24 Initialization Control 3 (Word 0x24)
These words control the general initialization values of the LAN port.
Bit Name
Default HW
Mode
Description
15:8 LAN D0 Power 0x0
The value in this field is reflected in the PCI Power Management Data Register of
the PCIe function for D0 power consumption and dissipation (Data_Select = 0 or
4). Power is defined in 100 mW units. The power also includes the external logic
required for the LAN function. Refer to Section 9.4.1.4.
7:5
PCIe Function
Common Power
0x0
The value in this field is reflected in the PCI Power Management Data register of
the PCIe function when the Data_Select field is set to 8 (common function). The
MSBs in the data register that reflects the power values are padded with zeros.
Refer to Section 9.4.1.4.
4:0 LAN D3 Power 0x0
The value in this field is reflected in the PCI Power Management Data register of
the PCIe function for D3 power consumption and dissipation (Data_Select = 3 or
7). Power is defined in 100 mW units. The power also includes the external logic
required for the function. The MSBs in the data register that reflects the power
values are padded with zeros. Refer to Section 9.4.1.4.
Bit Name
Default HW
Mode
Description
15
SerDes Energy
Source
0b
SerDes Energy Source Detection
When set to 0b, source is internal SerDes Rx circuitry for electrical idle or link-up
indication.
When set to 1b, source is external SRDS_[n]_SIG_DET signal for electrical idle or
Link-up indication.
This bit also indicates the source of the signal detect while establishing a link in
SerDes mode.
This bit sets the default value of the CONNSW.ENRGSRC bit. Refer to Section 8.2.6.
14 2 wires SFP Enable 0b
2-wire SFP Interface Enable
This bit is used to enable interfacing an external PHY either VIA the MDIO or I
2
C
interface
0b = Disabled. When disabled, the 2-wire I/F pads are isolated.
1b = Enabled.
Used to set the default value of CTRL_EXT.I2C Enabled. Refer to Section 8.2.3.
13 ILOS 0b
Invert Loss-of-Signal (LOS/LINK) Signal
Default setting for the loss-of-signal polarity bit (CTRL[7]). Refer to Section 8.2.1.
12:11 Reserved 00b Reserved.
10 APM Enable 0b
Initial value of Advanced Power Management Wake Up Enable bit in the Wake Up
Control (WUC.APME) register. Mapped to CTRL[6] and to WUC[0]. Refer to
Section 8.2.1 and Section 8.21.1.
Note: The disabled port that has the PHY_in_LAN_disable Flash bit (refer to
Section 6.2.21), set to 1b, the APM Enable Flash bit should be 0b.
9
Enable Automatic
Crossover
1b
When set, the device automatically determines whether or not it needs to cross over
between pairs so that an external cross-over cable is not required.
Used to set the default value to IPCNFG bit 0.
8ACBYP 0b
Bypass On-chip AC Coupling in Rx Input Buffers
ACBYP = 0 - Normal mode; on-chip AC coupling present.
ACBYP = 1 - On-chip AC coupling bypassed.
7 LAN Boot Disable 1b A value of 1b disables the Expansion ROM BAR in the PCI configuration space.
6EN_APM_D00b
Enable APM Wake On D0
0b = Enable APM wake only when function is in D3 and WUC.APME is set to 1b.
1b = Always enable APM wake when WUC.APME is set to 1b.
Loaded to the WUC.EN_APM_D0 bit (refer to Section 8.21.1).