Data Sheet

Flash Map—Ethernet Controller I210
199
12
Disable 100 in
non-D0a
0b
Disables 1000 Mb/s and 100 Mb/s operation in non-D0a states (refer to
Section 3.7.8.5.4).
Sets default value of PHPM.Disable 100 bit in non-D0a mode.
11 Reserved 0b Reserved.
10 I2C_ON_SDP_EN 0b
When set to 1b, SDP pins 0 and 2 operate as I
2
C pins controlled by the I2CCMD
and I2CPARAMS registers set.
Used to set the default value of CTRL_EXT.I2C over SDP Enabled. Refer to
Section 8.2.3.
9 SDPDIR[1] 0b
SDP1 Pin – Initial Direction
This bit configures the initial hardware value of the SDP1_IODIR bit in the Device
Control (CTRL) register following power up. See section 8.2.1 .
8 SDPDIR[0] 0b
SDP0 Pin – Initial Direction
This bit configures the initial hardware value of the SDP0_IODIR bit in the Device
Control (CTRL) register following power up. See section 8.2.1 .
7 SDPVAL[3] 0b
SDP3 Pin – Initial Output Value
This bit configures the initial power-on value output on SDP3 (when configured as
an output) by configuring the initial hardware value of the SDP3_DATA bit in the
Extended Device Control (CTRL_EXT) register after power up. See section 8.2.3 .
6 SDPVAL[2] 0b
SDP2 Pin – Initial Output Value
This bit configures the initial power-on value output on SDP2 (when configured as
an output) by configuring the initial hardware value of the SDP2_DATA bit in the
Extended Device Control (CTRL_EXT) register after power up. See section 8.2.3 .
5WD_SDP00b
When set, SDP[0] is used as a watchdog timeout indication. When reset, it is used
as an SDP (as defined in bits 8 and 0). See section 8.2.1 .
4Giga Disable0b
When set, GbE operation is disabled. A usage example for this bit is to disable GbE
operation if system power limits are exceeded (refer to Section 3.7.8.5.4).
3
Disable 1000 in
non-D0a
1b Disables 1000 Mb/s operation in non-D0a states (refer to Section 3.7.8.5.4).
2
D3COLD_WAKEU
P_ADVEN
1b
Controls reporting of D3 Cold wake-up support in the Power Management
Capabilities (PMC) configuration register (refer to Section 9.4.1.3).
In addition, bit is loaded to CTRL.ADVD3WUC (refer to Section 8.2.1).
When set, D3Cold wake up capability is advertised based on whether AUX_PWR
pin is connected to 3.3V to advertise presence of auxiliary power (yes, if AUX_PWR
is indicated, no otherwise). When set to 0b, D3Cold wake up capability is not
advertised even if AUX_PWR presence is indicated.
If full 1 GbE operation in D3 state is desired but the system's power requirements
in this mode would exceed the D3Cold wake up enabled specification limit (375 mA
at 3.3V), this bit can be used to prevent the capability from being advertised to
the system.
1 SDPVAL[1] 0b
SDP1 Pin – Initial Output Value
This bit configures the initial power-on value output on SDP1 (when configured as
an output) by configuring the initial hardware value of the SDP1_DATA bit in the
Device Control (CTRL) register after power up. See section 8.2.1 .
0 SDPVAL[0] 0b
SDP0 Pin – Initial Output Value
This bit configures the initial power-on value output on SDP0 (when configured as
an output) by configuring the initial hardware value of the SDP0_DATA
bit in the
Device Control (CTRL) register after power up. See section 8.2.1 .
Bit Name
Default HW
Mode
Description