Data Sheet

Ethernet Controller I210 —Flash Map
198
6.2.20 LED0,2 Configuration Defaults (Word 0x1F)
These Flash words specify the hardware defaults for the LEDCTL register fields controlling the LED
(LINK_UP) and LED2 (LINK_100) output behaviors. These words control the LED behavior of the LAN
port.
6.2.21 Software Defined Pins Control (Word 0x20)
These words at offset 0x20 from start of relevant Flash section are used to configure initial settings of
software defined pins (SDPs) for the LAN.
Bit Name
Default HW
Mode
Description
15 LED2 Blink 0b
Initial value of LED2_BLINK field.
0b = Non-blinking.
Refer to Section 8.2.8 and Section 7.5.
14 LED2 Invert 0b
Initial value of LED2_IVRT field.
0b = Active-low output.
Refer to Section 8.2.8 and Section 7.5.
13:12 Reserved 0x0 Reserved
11:8 LED2 Mode 0111b
Initial value of the LED2_MODE field specifying what event/state/pattern is
displayed on the LED2 (LINK_1000) output. A value of 0111b (0x7) indicates 1000
Mb/s operation.
Refer to Section 8.2.8 and Section 7.5.
7LED0 Blink 0b
Initial value of LED0_BLINK field.
0b = Non-blinking.
Refer to Section 8.2.8 and Section 7.5.
6 LED0 Invert 0b
Initial value of LED0_IVRT field.
0b = Active-low output.
Refer to Section 8.2.8 and Section 7.5.
5 Global Blink Mode 0b
Global Blink Mode
0b = Blink at 200 ms on and 200 ms off.
1b = Blink at 83 ms on and 83 ms off.
Refer to Section 8.2.8 and Section 7.5.
4 Reserved 0b Reserved. Set to 0b.
3:0 LED0 Mode 0110b
Initial value of the LED0_MODE field specifying what event/state/pattern is
displayed on the LED0 (LINK_100) output. A value of 0100b (0x4) indicates the
LINK_100 state.
Refer to Section 8.2.8 and Section 7.5.
Bit Name
Default HW
Mode
Description
15 SDPDIR[3] 0b
SDP3 Pin – Initial Direction
This bit configures the initial hardware value of the SDP3_IODIR bit in the
Extended Device Control (CTRL_EXT) register following power up. Refer to
Section 8.2.3.
14 SDPDIR[2] 0b
SDP2 Pin – Initial Direction
This bit configures the initial hardware value of the SDP2_IODIR bit in the
Extended Device Control (CTRL_EXT) register following power up. See section
8.2.3 .
13
PHY_in_LAN_disa
ble
1b
Determines the behavior of the MAC and PHY when the LAN port is disabled
through an external pin.
0b = MAC and PHY are kept functional in device off mode (to support
manageability).
1b = MAC and PHY are powered down in device off mode (manageability cannot
access the network through this port).