Data Sheet

Ethernet Controller I210 —Flash Map
196
6.2.16 PCIe Init Configuration 3 Word (Word 0x1A)
This word is used to set defaults for some internal PCIe registers.
6.2.17 PCIe Control 1 (Word 0x1B)
This word is used to configure initial settings for PCIe default functionality.
Bit Name
Default HW
Mode
Description
15:13 AER Capability Version 0x2
AER Capability Version Number
PCIe AER extended capability version number.
Refer to Section 9.5.1.1.
12 Cache_Lsize 0b
Cache Line Size
0b = 64 bytes.
1b = 128 bytes.
This bit defines the cache line size reported in the PCIe Mandatory
Configuration register area. Refer to Section 9.3.7.
11:10 GIO_Cap 10b
PCIe Capability Version
The value of this field is reflected in the two LSBs of the capability version in
the PCIe CAP register (config space – offset 0xA2).
This field must be set to 10b to use extended configuration capability.
Note that this is not the PCIe version. It is the PCIe capability version. This
version is a field in the PCIe capability structure and is not the same as the
PCIe version. It changes only when the content of the capability structure
changes. For example, PCIe 1.0, 1.0a, and 1.1 all have a capability version of
one. PCIe 2.0 has a version of two because it added registers to the
capabilities structures. Refer to Section 9.4.6.3.
9:8 Max Payload Size 10b
Default Packet Size
00b = 128 bytes.
01b = 256 bytes.
10b = 512 bytes.
11b = Reserved.
Loaded to two LSB bits of the Max Payload Size Supported field in the Device
Capabilities register (refer to Section 9.4.6.4).
7:4 Reserved Reserved.
3:2 Act_Stat_PM_Sup 11b
Determines support for active state link power management.
Loaded into the PCIe Active State Link PM Support register. Refer to
Section 9.4.6.7.
1 Slot_Clock_Cfg 1b
When set, the I210 uses the PCIe reference clock supplied on the connector
(for add-in solutions).
0 Reserved Reserved.
Bit Name
Default HW
Mode
Description
15:12 Reserved 0x0 Reserved.
11 Disable ACLs 0b If set, the ACLs on the PCIe VDMs are disabled.
10 No_Soft_Reset 1b
No_Soft_Reset
This bit defines the behavior of the I210 when a transition from the D3hot to D0
power state occurs. When this bit is set, no internal reset is issued when making
a transition from D3hot to D0. Value is loaded to the No_Soft_Reset bit in the
PMCSR register (refer to Section 9.4.1.4).
9:0 Reserved 0 Reserved.