Data Sheet

Flash Map—Ethernet Controller I210
195
6.2.15 PCIe Init Configuration 2 Word (Word 0x19)
This word is used to set defaults for some internal PCIe configuration registers.
11:6 Reserved 0b Reserved.
5:3 L0s G1 Sep Exit Latency 111b
L0s Exit Latency G1S
Loaded to L0s Exit Latency field in the Link Capabilities register in
the PCIe Configuration registers in PCIe v2.1 (2.5GT/s) system at a
separate clock setting.
2:0 L0s G1 Com Exit Latency 101b
L0s Exit Latency G1C
Loaded to L0s Exit Latency field in the Link Capabilities register in
the PCIe Configuration registers in PCIe v2.1 (2.5GT/s) system at a
Common clock setting.
Bit Name
Default HW
Mode
Description
15 Reserved Reserved.
14 IO_Sup 1b
I/O Support (affects I/O BAR request)
When set to 1b, I/O is supported. When cleared the I/O Access Enable bit in the
Command Reg in the Mandatory PCI Configuration area is RO with a value of 0b.
For additional information on CSR access via I/O address space, see Section 8.1.1.5.
13 CSR_conf_en 1b
Enable CSR Access Via Configuration Space
When set, enables CSR access via the configuration registers located at configuration
address space 0x98 and 0x9C.
For additional information on CSR access via configuration address space, see
Section 8.1.1.6.
12
Serial Number
Enable
1b
Serial Number Capability Enable
Should be set to 1b.
11:0 Reserved 0x0 Reserved.
Bits Name
Default HW
Mode
Description