Data Sheet

Ethernet Controller I210 —Flash Map
194
6.2.11 PCIe L1 Exit Latencies (Word 0x14)
6.2.12 PCIe Completion Timeout Configuration (Word 0x15)
6.2.13 MSI-X Configuration (Word 0x16)
These words configure MSI-X functionality for the LAN.
6.2.14 PCIe Init Configuration 1 (Word 0x18)
This word is used to define L0s exit latencies.
Bits Name
Default HW
Mode
Description
15 Reserved 1b Reserved.
14:12 L1_Act_Acc_Latency 110b
Loaded to the Endpoint L1 Acceptable Latency field in Device
Capabilities in the PCIe Configuration registers at power up.
11:6 Reserved 0b Reserved.
5:3 L1 G1 Sep exit latency 100b
L1 exit latency G1S. Loaded to Link Capabilities -> L1 Exit Latency
at PCIe v2.1 (2.5GT/s) system in a separate clock setting.
2:0 L1 G1 Com exit latency 100b
L1 exit latency G1C. Loaded to Link Capabilities -> L1 Exit Latency
at PCIe v2.1 (2.5GT/s) system in a common clock setting.
Bit Name
Default HW
Mode
Description
15:5 Reserved Reserved.
4
Completion Timeout
Resend
0b
When set, enables to resend a request once the completion timeout expired.
0b = Do not re-send request on completion timeout.
1b = Re-send request on completion timeout. Refer to Section 8.6.1.
3:0 Reserved 0x0 Reserved.
Bit Name
Default HW
Mode
Description
15:11 MSI_X_N 0x4
This field specifies the number of entries in MSI-X tables of the relevant LAN.
The range is 0-4. MSI_X_N is equal to the number of entries minus one. Refer to
Section 9.4.3.3.
10 MSI Mask 1b
MSI Per-vector Masking Setting
This bit is loaded to the masking bit (bit 8) in the Message Control word of the
MSI Configuration Capability structure.
9:0 Reserved 0x0 Reserved.
Bits Name
Default HW
Mode
Description
15 Reserved 0b Reserved.
14:12 L0s Acceptable Latency 011b
Loaded to the Endpoint L0s Acceptable Latency field in the Device
Capabilities in the PCIe configuration registers at power up.