Data Sheet

Flash Map—Ethernet Controller I210
193
6.2.9 Flash Validity and Protected Fields (Word 0x12)
6.2.10 Initialization Control 4 (Word 0x13)
These words control general initialization values of the LAN port.
4
Unprotect After
Reset
0b
When set, the Flash internal protection is removed after reset - operating the
device in the non-secured mode.
3 SST Mode 0b
When set, the device operates the Flash device pins as if it was an SST Flash part.
Meaningful only when bit 8 is set or when the Flash part was not found in the
Flash devices table embedded in the firmware image.
2:0 FL_SIZE 000b
Flash Size.
Indicates the size of the Flash device according to the following equation:
Size = 64 KB * 2 ** “FL_SIZE”.
Supported Flash sizes:
000b = 0 - no Flash device
101b = 2 MB
110b = 4 MB
111b = 8 MB
Bit Name
Default HW
Mode
Description
15:14 NVM Validity
The Validity field indicates to the I210 that there is a valid Flash present. If the
field is 01b, Flash read is performed, otherwise the other bits in this word are
ignored, no further Flash read is performed, and hardware default values are used
for the configuration space IDs.
13 NVM_SEC_EN 0b
Flash Security Enable.
0b - Operate the device in the blank Flash programming mode (not performing
any of the Flash security checks).
1b - Flash security protection scheme is enabled (provided the device is not
operated in the blank Flash programming mode by another mean). Refer to
Section 3.3.1.2. After writing this bit to 1b, a firmware reset or a power cycle is
required before the Flash security mode is entered.
12:11 Reserved 0x0 Reserved.
10:0
Start of 2nd
Protected Area
0x7FF
Defines the start of the 2nd area in the Flash that is RO. The resolution is one
word and can be up to word address 0x7FF. The area’s end coincides with the
shadow RAM’s end.
Bit Name
Default HW
Mode
Description
15:8 Reserved 0x0 Reserved.
7SPD Enable 1b
Smart Power Down
When set, enables internal PHY smart power down mode (refer to
Section 3.7.8.5.5).
6LPLU 1b
Low Power Link Up
Enables a decrease in link speed in non-D0a states when power policy and power
management states dictate it (refer to Section 3.7.8.5.4).
5:1 PHY_ADD 0x00 PHY address. Value loaded to the MDICNFG.PHYADD field. Refer to Section 8.2.5.
0 DEV_RST_EN 1b
Enable software reset (CTRL.DEV_RST) generation to the LAN port (refer to
Section 4.3).