Data Sheet

Ethernet Controller I210 —Flash Map
192
6.2.8 Flash Device Size (Word 0x11)
8TX_LPI_EN 0b
Enable entry into EEE LPI on TX path. Refer to Section 8.25.12.
0b = Disable entry into EEE LPI on Tx path.
1b = Enable entry into EEE LPI on Tx path.
7
MAC Clock Gating
Enable
0b
Enables the MAC clock gating power saving mode. Mapped to STATUS[31]. This
bit is relevant only if the Enable Dynamic MAC Clock Gating bit is set. Refer to
Section 8.2.2.
6
PHY Power Down
Enable
1b
When set, enables the internal PHY to enter a low-power state (refer to
Section 3.7.8.5). This bit is mapped to CTRL_EXT[20] (refer to Section 8.2.3).
5 10BASE-TE 0b
Enable Low Amplitude 10BASE-T Operation
Setting this bit enables the I210 to operate in IEEE802.3az 10BASE-Te low
power operation. Bit is loaded to IPCNFG.10BASE-TE register bit (refer to
Section 8.27.1).
0b = 10BASE-Te operation disabled.
1b = 10BASE-Te operation enabled.
Note: When operating in 10BASE-T mode and bit is set supported cable length
is reduced.
4 Reserved 0b Reserved
3
Enable Dynamic
MAC Clock Gating
0b
When set, enables dynamic MAC clock gating mechanism. Refer to
Section 8.2.3.
2
SerDes Low Power
Enable
0b
When set, enables the SerDes to enter a low power state when the function is in
Dr state. Refer to Chapter 5.0 and Section 8.2.3.
1 EEE_1G_AN 1b
Report EEE 1 GbE Capability in Auto-negotiation. Refer to Section 8.27.1.
0b = Do not report EEE 1 GbE capability in auto-negotiation.
1b = Report EEE 1 GbE capability in auto-negotiation.
0 EEE_100M_AN 1b
Report EEE 100 Mb/s Capability in Auto-negotiation. Refer to Section 8.27.1.
0b = Do not report EEE 100 Mb/s capability in auto-negotiation.
1b = Report EEE 100 Mb/s capability in auto-negotiation.
Bit Name
Default HW
Mode
Description
15:9 Reserved 0b Reserved
8
Flash Defaults
from Word 0x11
0b
When set, the Flash settings are taken from bits 7:3 of this Flash word - even if
the Flash part was found in the Flash devices table embedded in the firmware
image. This is useful for diagnostics.
7
Fast Read
Support
0b
When set, the fast read sequence is used when reading from the Flash part.
Meaningful only when bit 8 is set or when the Flash part was not found in the
Flash devices table embedded in the firmware image.
6:5 Flash Speed 00b
Indicates the frequency of the clock provided to Flash.
00b = Clock is 15.125 MHz,
01b = Clock is 31.25 MHz,
10b = Clock is 62.5 MHz,
11b = Reserved
Meaningful only when bit 8 is set or when the Flash part was not found in the
Flash devices table embedded in the firmware image.
Bit Name
Default HW
Mode
Description