Data Sheet

Introduction—Ethernet Controller I210
19
1.8.2 Receive Data Flow
Table 1-12 lists a high level description of all data/control transformation steps needed for receiving
Ethernet packets.
Table 1-11. Transmit Data Flow
Step Description
1
The host creates a descriptor ring and configures one of the I210's transmit queues with the address location,
length, head and tail pointers of the ring (one of 4 available Tx queues).
2
The host is requested by the TCP/IP stack to transmit a packet, it gets the packet data within one or more data
buffers.
3
The host initializes descriptor(s) that point to the data buffer(s) and have additional control parameters that
describe the needed hardware functionality. The host places that descriptor in the correct location at the
appropriate Tx ring.
4 The host updates the appropriate queue tail pointer (TDT)
5
The I210's DMA senses a change of a specific TDT and as a result sends a PCIe request to fetch the descriptor(s)
from host memory.
6
The descriptor(s) content is received in a PCIe read completion and is written to the appropriate location in the
descriptor queue internal cache.
7
The DMA fetches the next descriptor from the internal cache and processes its content. As a result, the DMA sends
PCIe requests to fetch the packet data from system memory.
8
The packet data is received from PCIe completions and passes through the transmit DMA that performs all
programmed data manipulations (various CPU off loading tasks as checksum off load, TSO off load, etc.) on the
packet data on the fly.
9
While the packet is passing through the DMA, it is stored into the transmit FIFO. After the entire packet is stored in
the transmit FIFO, it is forwarded to the transmit switch module.
10
The transmit switch arbitrates between host and management packets and eventually forwards the packet to the
MAC.
11 The MAC appends the L2 CRC to the packet and sends the packet to the line using a pre-configured interface.
12 When all the PCIe completions for a given packet are done, the DMA updates the appropriate descriptor(s).
13
After enough descriptors are gathered for write back or the interrupt moderation timer expires, the descriptors are
written back to host memory using PCIe posted writes. Alternatively, the head pointer can only be written back.
14
After the interrupt moderation timer expires, an interrupt is generated to notify the host device driver that the
specific packet has been read to the I210 and the driver can release the buffers.
Table 1-12. Receive Data Flow
Step Description
1
The host creates a descriptor ring and configures one of the I210's receive queues with the address location,
length, head, and tail pointers of the ring (one of 4 available Rx queues).
2
The host initializes descriptors that point to empty data buffers. The host places these descriptors in the correct
location at the appropriate Rx ring.
3 The host updates the appropriate queue tail pointer (RDT).
4
The I210's DMA senses a change of a specific RDT and as a result sends a PCIe request to fetch the descriptors
from host memory.
5
The descriptors content is received in a PCIe read completion and is written to the appropriate location in the
descriptor queue internal cache.
6 A packet enters the Rx MAC. The Rx MAC checks the CRC of the packet.
7 The MAC forwards the packet to an Rx filter.
8
If the packet matches the pre-programmed criteria of the Rx filtering, it is forwarded to the Rx FIFO. VLAN and
CRC are optionally stripped from the packet and L3/L4 checksum are checked and the destination queue is fixed.
9
The receive DMA fetches the next descriptor from the internal cache of the appropriate queue to be used for the
next received packet.