Data Sheet

Flash Map—Ethernet Controller I210
191
6.2.3 Subsystem ID (Word 0x0B)
If the Load Subsystem IDs in Initialization Control Word 1 Flash word is set, the Subsystem ID word in
the Common section is read in to initialize the PCIe Subsystem ID. Default value is 0x0 (refer to
Section 9.3.14).
6.2.4 Subsystem Vendor ID (Word 0x0C)
If the Load Subsystem IDs bit in Initialization Control Word 1 Flash word is set, the Subsystem Vendor
ID word in the Common section is read in to initialize the PCIe Subsystem Vendor ID. The default value
is 0x8086 (refer to Section 9.3.13).
6.2.5 Device ID (Word 0x0D)
If the Load Vendor/Device IDs bit in Initialization Control Word 1 is set, the Device ID Flash word is
read in from the Common section to initialize the device ID of the LAN function. The default value is
0x1533 for the I210 (copper only SKU) (for other SKUs refer to Section 9.3.2).
6.2.6 Vendor ID (Word 0x0E)
If the Load Vendor/Device IDs bit in Initialization Control Word 1 Flash word is set, this word is read in
to initialize the PCIe Vendor ID. The default value is 0x8086 (refer to Section 9.3.1).
Note: If a value of 0xFFFF is placed in the Vendor ID Flash word, the value in the PCIe Vendor ID
register returns to the default 0x8086 value. This functionality is implemented to avoid a
system hang situation.
6.2.7 Initialization Control Word 2 (Word 0x0F)
The Initialization Control Word 2 read by the I210, contains additional initialization values that:
• Set defaults for some internal registers
• Enable/disable specific features
Bit Name
Default HW
Mode
Description
15 APM PME# Enable 0b
Initial value of the Assert PME On APM Wakeup bit in the Wake Up Control
(WUC.APMPME) register. Refer to Section 8.21.1.
14 PCS Parallel Detect 1b
Enables PCS parallel detect. Mapped to the PCS_LCTL.AN TIMEOUT EN bit. Refer
to Section 8.17.2.
Note: Bit should be 0b only when the port operates in SGMII mode
(CTRL_EXT.LINK_MODE = 10b).
13:12 Pause Capability 11b
Desired pause capability for advertised configuration base page. Mapped to
PCS_ANADV.ASM. Refer to Section 8.17.4.
11 ANE 0b
Auto-Negotiation Enable
Mapped to PCS_LCTL.AN_ENABLE. Refer to Section 8.17.2.
Note: Bit should be 0b when the port operates in internal copper PHY mode and
1000BASE-KX modes.
10 FRCSPD 0b
Force Speed
Default setting for the Force Speed bit in the Device Control register
(CTRL[11]). Refer to Section 8.2.1
9FD 1b
Full-Duplex
Default setting for duplex setting. Mapped to CTRL[0]. Refer to Section 8.2.1