Data Sheet

Ethernet Controller I210 —Flash Map
190
Bit Name Default HW Mode Description
15 iNVM 0b
14 GPAR_EN 0b
1
1. This bit must be set to 1b in every Flash image.
Global Parity Enable
Enables parity checking of all the I210 memories.
0b = Disable parity check
1b = Enable parity check according to the per RAM parity enable bits.
Loaded to the PCIEERRCTL register (refer to Section 8.24.4) only at
LAN_PWR_GOOD events.
13 LTR_EN 1b
LTR Capabilities Reporting Enable
0b = Do not report LTR support in the PCIe configuration Device
Capabilities 2 register.
1b = Report LTR support in the PCIe configuration Device Capabilities 2
register.
Defines the default setting of LTR capabilities reporting (refer to
Section 9.4.6.11).
12 VPD_EN 0b
VPD Capability Enable.
0b - Do not report VPD support.
1b - Report VPD support.
This bit must be set in Flash images only once the VPD area is
programmed with a valid contents.
11 HI_DISABLE 0b
Host Interface Disable.
This bit is meaningful only for the I211 SKU.
1b = Do not allow the host to download firmware code.
0b = The host is allowed to download firmware code using the flow
described in Section 3.4.6.
10:7 Reserved 0x0 Reserved
6 SDP_DDOFF_EN 0b
When set, SDP I/Os keep their value and direction when the I210 enters
Dynamic Device Off mode.
When cleared, SDP I/Os move to HighZ plus pull-up mode in Dynamic
Device Off mode.
This bit is meaningless if Dynamic Device Off mode is disabled in Flash
word 0x1E.
5
Deadlock Timeout
Enable
1b
If set, a software device driver granted access to the Flash that does not
toggle the Flash interface for more than eight seconds will have the
grant revoked. Refer to Section 3.3.7. This bit also enables EERD and
EEMNGCTL timeout if the Flash is not responding to status read.
4
LAN PLL Shutdown
Enable
0b
When set, enables shutting down the PHY PLL in low-power states when
the internal PHY is powered down (such as link disconnect). When
cleared, the PHY PLL is not shut down in a low-power state.
3 Power Management 1b
0b = Power management registers set to read only. In this mode, the
I210 does not execute a hardware transition to D3.
1b = Full support for power management. For normal operation, this bit
must be set to 1b.
See section 9.4.1 .
2
DMA Clock Gating
Disabled
1b When set, disables DMA clock gating power saving mode.
1 Load Subsystem IDs 1b
When this bit is set to 1b the I210 loads its PCIe subsystem ID and
subsystem vendor ID from the Flash (Subsystem ID and Subsystem
Vendor ID Flash words).
0
Load Vendor/Device
IDs
1b
When set to 1b the I210 loads its PCIe Device IDs from the Flash
(Device ID Flash words) and the PCIe Vendor ID from the Flash.