Data Sheet

Power Management—Ethernet Controller I210
183
3. If the I210 reported following PCIe link-up latency tolerance requirements with any requirement bit
set and the LTR Mechanism Enable bit in the PCIe configuration space is cleared, the I210 sends a
new LTR message with all the requirement bits clear.
4. The I210 sends a LTR message with the value placed in the LTRMAXV register when either one of
following conditions exist:
a. Software set the LTRC.LTR_MAX register bit.
b. Rx EEE LPI state is detected on the Ethernet link and LTRC.EEEMS_EN is set (see
Section 3.7.7.4).
5. Otherwise, the I210 sends a LTR message with a minimum value.
Note: In all cases, the maximum LTR value sent by the I210 does not exceed the maximum latency
values in the Max No-Snoop Latency and Max Snoop Latency Registers in the LTR capability
structure of function 0.
Figure 5-7 shows the I210 LTR message generation flow.