Data Sheet

Ethernet Controller I210 —Power Management
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In systems that don’t support OBFF, asynchronous device activity prevents optimal power management
of memory, CPU, and other Root Complex (RC) internal circuitry because device activity tends to be
misaligned with respect to other devices and with respect to the natural activity of the system. The
PCIe OBFF mechanism implemented in the I210 enables synchronizing device activity and optimizing
system power management.
This OBFF indication is a hint, as all back devices are still permitted to initiate bus mastering and
interrupt traffic at any time, although this negatively impacts the platform power and should be avoided
as much as possible. In such cases, the platform can use OBFF to signal other platform devices so as to
minimize the negative impact.
OBFF states:
• Active: The CPU is in C0 with the path to memory open. The I210 should execute all DMA traffic/
activity and interrupts as needed
• OBFF: The CPU is not executing instructions (such as CPU is in Cx) but the path to memory is open.
The I210 should execute all opportunistic bus master traffic but hold all opportunistic interrupts
• IDLE: The CPU is in Cx with the path to memory closed. The I210 should hold all opportunistic
traffic and interrupts as possible
OBFF events are signaled using the PE_WAKE_N signal on platforms supporting this topology. OBFF
prevents needless link reactivation for a common case where most devices have no need to perform
bus master or interrupts.
Note: The I210 only supports OBFF events signaled using the PE_WAKE_N signal. OBFF pulse timing
can be configured via the PCIEOBFF register (See Section 8.6.18).
Support for OBFF is reported in the PCIe Device Capabilities 2 configuration register. The OBFF
message receiving mechanism (PE_WAKE_N or PCIe message) is defined in the PCIe Device Control 2
configuration register. OBFF support is enabled by the OBFF Supported field in the PCIe Control 1 Flash
word.
5.10 Latency Tolerance Reporting (LTR)
The I210 generates PCIe LTR messages to report service latency requirements for memory reads and
writes to the RC for system power management.
The I210 reports either minimum latency tolerance, maximum latency tolerance or no latency tolerance
requirements as a function of link, LAN port and function status. Minimum and maximum latency
tolerance values are programmed in the LTRMINV and LTRMAXV registers, respectively, per PF by the
software device driver to optimize power consumption without incurring packet loss due to receive
buffer overflow.
5.10.1 LTR Algorithm
The I210 sends LTR messages according to the following algorithm when the capability is enabled in the
LTR capability structure of function 0 located in PCIe configuration space:
1. When link disconnected or port is disabled (transmit and receive activity not enabled) and the
LTRC.LNKDLS_EN and LTRC.PDLS_EN bits are set. respectively, the I210 sends a LTR PCIe message
with LTR requirement bits cleared, to indicate that no latency tolerance requirements exists.
2. If the I210 reported following PCIe link-up latency tolerance requirements with any requirement bit
set in the PCIe LTR message and all enabled functions where placed in D3 low power state via the
PMCSR register, the I210 sends a new LTR message with all the requirement bits clear.