Data Sheet

Power Management—Ethernet Controller I210
181
5.8.3 Conditions to Exit DMA Coalescing
5.8.3.1 Exiting DMA Coalescing
When the I210 is in DMA coalescing operating mode, DMA coalescing mode is exited when one of the
following events occurs:
1. Amount of data in the internal receive buffer passed the DMACR.DMACTHR threshold or when OBFF
is enabled and in OBFF or “OBFF Active” states, the amount of data in internal receive buffer passed
the DOBFFCTL.OBFFTHR threshold.
2. Empty space in the internal transmit buffer is above the value defined in the DMCTXTH.DMCTTHR
field and available transmit descriptors exist.
3. A high priority packet was received (see Section 7.3.6 for a definition of high priority packets). A
high priority packet is a packet that generates an immediate interrupt, as defined in the IMIR[n],
IMIREXT[n] or IMIRVP registers.
4. A received packet destined to a high priority queue (SRRCTL[n].DMACQ_Dis =1b) was detected.
5. DMA coalescing watchdog timer defined in the DMACR.DMACWT field expires as a result of the
following occurrences not being serviced for the duration defined in the DMACR.DMACWT field:
— An Rx packet was received in the internal buffer.
— An interrupt is pending.
— A descriptor write-back is pending.
— On-chip transmit tail pointer was updated.
6. Received data rate detected is lower than defined in the DMCRTRH.UTRESH field.
7. DMA coalescing is disabled (DMACR.DMAC_EN = 0b).
8. Software initiates a move out of DMA coalescing by writing 1b to the DMACR.EXIT_DC self-clearing
bit.
9. MC to OS traffic if the DMACR.DC_BMC2OSW_EN bit is programmed to 0b.
10. Management indication are enabled through DMCTLX.EN_MNG_IND and the amount of data
buffered in the management buffer exceeds DMCMNGTH.DMCMNGTHR.
Notes:
1. Even when conditions for DMA coalescing do not exist, the I210 continues to be in a low power PCIe
link state (L0s or L1) if there is no requirement for PCIe access.
2. If a PCIe PME wake message needs to be sent, the PCIe link moves from an L1 low power state to
L0 to send the message but DMA remains in the DMA coalescing state.
3. Pending interrupts or pending descriptor write-back operations do not cause the I210 to move out
of the DMA coalescing state.
5.9 OBFF
During active block I/O workloads, devices generate cycles as needed that statistically creates a
random amount of traffic that keeps system busses and resources from efficiently entering their low
power states. OBFF mode attempts to organize this random traffic and make it more orderly and bursty
at a platform level in order to enable system busses and resources to enter low power states even
under moderate to heavy loads. The technique is to organize all devices such that they all flush or fill
their FIFOs at the same time and is referred to as OBFF.