Data Sheet

Ethernet Controller I210 —Power Management
180
8. DOBFFCTL.OBFFTHR field to set the low receive threshold that causes move out of DMA coalescing
operating mode when the PCIe is in OBFF or OBFF Active states. Receive watermark programmed
must be lower than DMACR.DMACTHR.
9. DMCTLX.EN_MNG_IND bit should be set to 1b to enable management indication impact on DMA
Coalescing and OBFF operating modes. This bit also enables DMA coalescing and OBFF impact on
MCTP over PCIe traffic.
10. DMCMNGTH.DMCMNGTHR field to set the threshold for the management buffer that causes move
out of DMA coalescing operating mode.
Notes:
1. The values of DMACR.DMACTHR and FCRTC.RTH_Coal should be set so that XOFF packet
generation is avoided. In DMA coalescing mode, when the transmit buffer is empty, the XOFF flow
control threshold (FCRTC.RTH_Coal) value can be increased by the maximum jumbo frame size
compared to normal operation, where the high threshold is set by the FCRTH0 register.
2. When entering DMA coalescing mode, the value written in the FCRTH0 register is used to generate
XOFF flow control frames until the internal transmit buffer is empty. Once the internal transmit
buffer is empty the value written in the FCRTC.RTH_Coal field is used as a watermark for
generation of XOFF flow control frames.
3. The I210 transitions the link into L0s state once the PCIe link has been idle for a period of time
defined in the Latency_To_Enter_L0s field in the CSR Auto Configuration Power-Up Flash section
(see Section 6.3). The I210 will then transition the link into L1 state once the PCIe link has been in
L0s state for a further period as defined in the Latency_To_Enter_L1 field in the CSR Auto
Configuration Power-Up NVM section.
5.8.2 Entering DMA Coalescing Operating Mode
Enabling DMA coalescing operation by setting the DMACR.DMAC_EN bit to 1b. Power saving is achieved
since it increases the duration of these idle intervals. The Power Management Unit (PMU) on the
platform can use these idle intervals to reduce system power. In addition if OBFF is supported on PCIe
link additional system level power saving can be achieved by synchronizing activity of all devices on the
PCIe interface.
5.8.2.1 Entering DMA Coalescing
The I210 enters DMA coalescing when all of the following conditions exist:
1. DMA coalescing is enabled (DMACR.DMAC_EN = 1b).
2. Internal receive buffers (host and management if enabled) are empty.
3. There are no pending DMA operations.
4. None of the conditions defined in Section 5.8.3.1 to move out of DMA coalescing exist.
5. If OBFF is enabled in the PCIe config space and the OBFF state is IDLE or OBFF.
Before entering the DMA coalescing power saving mode, if the DMCTLX.DCFLUSH_DIS bit is
programmed to 0b, the I210:
• Flushes all pending interrupts that were delayed due to the Interrupt Throttling (ITR) mechanism.
• The I210 flushes all pending receive descriptor and transmit descriptor write backs and pre-fetch
available receive descriptors and transmit descriptors to the internal cache.