Data Sheet

Power Management—Ethernet Controller I210
179
The I210 exits DMA coalescing once the conditions defined in Section 5.8.3, to exit DMA coalescing,
exist.
5.8.1 DMA Coalescing Activation
To activate DMA coalescing functionality software driver should program the following fields:
1. DMACR.DMACTHR field to set the receive threshold that causes move out of DMA coalescing
operating mode. Receive watermark programmed should take into account latency tolerance
reported (See Section 5.10) and L1 to L0 latency to avoid receive buffer overflow when DMA
coalescing is enabled. A minimum of 70 us equivalent is recommended.
2. DMCTXTH.DMCTTHR field to set transmit threshold that causes move out of DMA coalescing
operating mode. Transmit watermark programmed should take into account latency tolerance
reported (See Section 5.10) and L1 to L0 latency to enable transmission of back-to-back packets
when DMA Coalescing is enabled.
3. DMACR.DMACWT field that defines a maximum timeout value for:
a. A receive packet to be stored in the internal receive buffer before the I210 moves a packet to
host memory.
b. Time to delay an interrupt that is not defined as an immediate interrupt in the IMIR[n],
IMIREXT[n] or IMIRVP registers, when other conditions specified in Section 5.8.3 to exit DMA
coalescing do not exist.
c. DMACR.DMACWT also defines maximum time to delay interrupts, that are not defined as
immediate interrupts when PCIe link is in OBFF state. In PCIe OBFF state System memory path
is available only for Device memory read/write bus master activities, but path for interrupts is
not available.
— Each time the I210 enters DMA coalescing, the internal DMA coalescing watchdog timer is re-
armed with the value placed in the DMACR.DMACWT field. When in DMA coalescing, the internal
watchdog timer starts to count when one of the following conditions occurs:
• A Rx packet is received in the internal buffer.
• An interrupt is pending.
• A descriptor write-back is pending.
Once an interval defined in the DMACR.DMACWT field has passed, the I210 exits DMA
coalescing and internal buffers, pending interrupts and pending descriptor write-backs are
flushed.
—The DMACR.DC_BMC2OSW_EN bits define if a BMC to OS traffic is delayed by the time defined
in the DMACR.DMACWT field when the I210 is in DMA coalescing state or if the traffic causes
immediate exit out of DMA coalescing.
4. DMCTLX.DCFLUSH_DIS to define if pending descriptor write-back flush and pending interrupt flush
should occur before entry into DMA coalescing state.
— When DMCTLX.DCFLUSH_DIS is set to 1b, any pending interrupts or descriptor write-back
operations do not cause the I210 to move out of a DMA coalescing state.
5. FCRTC.RTH_Coal field that defines a flow control receive high watermark for sending flow control
packets. The I210 uses the FCRTC.RTH_Coal threshold when:
— Flow control is enabled by setting the CTRL.TFCE bit.
— The I210 is in DMA coalescing mode.
— Internal transmit buffer is empty.
6. SRRCTL[n].DMACQ_Dis bit to define high priority queues. When a received packet is forwarded to a
queue with the SRRCTL[n].DMACQ_Dis bit set, the I210 moves immediately out of DMA coalescing
mode and executes a DMA operation to store the packet in host memory.
7. DMACR.DMAC_EN bit should be set to 1b to enable activation of DMA coalescing operating mode.