Data Sheet

Ethernet Controller I210 —Power Management
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— IPv6 MLD queries, with the Solicited-node Multicast Address placed in the IPv6 destination
address field of the IPv6 NS packets that are off-loaded by the I210 (as defined in RFC 2710
and RFC 3810). The MLDv2 Multicast Listener Report messages returned by firmware to MLDv2
Multicast Listener Query messages which concern the device, contain a Multicast Address
Record for each configured Solicited IPv6 addresses (up to 2). Other fields are returned as
follows:
• Number of Sources = 0 (no Source Address fields supplied)
• Record Type = 2 (MODE_IS_EXCLUDE)
• Aux Data Len = 0 (no Auxiliary Data fields supplied)
4. mDNS proxy offload
— Multicast DNS (mDNS) is used to advertise and locate services on the local network. Its proxy
offload requires the I210 to respond to mDNS queries as well as keeping the network
connectivity of a system while the system is in sleep state and wake the system when a service
is requested from the system.
— For more information on the I210 functionality and enablement for mDNS Proxy Offload. See
section 5.7.3
In addition to the D3 low power functionality, by setting D0_PROXY bit to 1b, the I210 enables these
features in D0 and enables the system to be in a low power S0x state for longer durations to increase
system power savings.
5.7.1 Protocol Offload Activation in D3
To enable protocol offload, the software device driver should implement the following steps before D3
entry:
1. Read MANC.MPROXYE bit to verify that proxying is supported by management.
2. Clear all pending proxy status bits in the Proxying Status (PROXYS) register.
3. Program the Proxying Filter Control (PROXYFC) register to indicate the type of packets that should
be forwarded to manageability for proxying and then program the necessary data to the IPv4/v6
Address Table (IP4AT, IP6AT) and the Flexible Host Filter Table (FHFT) registers.
4. Set the WUFC.FW_RST_WK bit to 1b to initiate a wake if firmware reset was issued when in D3
state and proxying information was lost.
5. Take ownership of the Management Host interface semaphore (SW_FW_SYNC.SW_MNG_SM
register bit) using the flow defined in Section 4.6.1 to send Protocol Offload information to
Firmware.
6. Read and clear the FWSTS.FWRI firmware reset indication bit.
— If a firmware reset was issued as reported in the FWSTS.FWRI bit, the software device driver
should clear the bit and then re-initialize the protocol offload list even if firmware keeps the
protocol offload list on a move from D3 to D0 (See note in Section 10.8.2.4.2.2).
7. Verify that the HICR.En bit (See Section 8.23.2) is set 1b, which indicates that the shared RAM
interface is available.
8. Write proxying information in the shared RAM interface located in addresses 0x8800-0x8EFF using
the format defined in Section 10.8.2.4.2. All addresses should be placed in networking order.
9. Once information is written into the shared RAM software should set the HICR.C bit to 1b.
10. Poll the HICR.C bit until bit is cleared by firmware indicating that the command was processed and
verified that the command completed successfully by checking that the HICR.SV bit was set.
11. Read the firmware response from the shared RAM to verify that data was received correctly.
12. Return to 8. if additional commands need to be sent to Firmware.