Data Sheet
Ethernet Controller I210 —Power Management
170
5.5.5 Timing Requirements
The I210 requires the following start-up and power state transitions.
5.5.6 Timing Guarantees
The I210 guarantees the following start-up and power state transition related timing parameters.
5.6 Wake Up
The I210 supports two modes of wake-up management:
1. Advanced Power Management (APM) wake up
2. ACPI/PCIe defined wake up
The usual model is to activate one mode at a time but not both modes together. If both modes are
activated, the I210 might wake up the system on unexpected events. For example, if APM is enabled
together with the ACPI/PCIe Magic packet in the WUFC register, a magic packet might wake up the
system even if APM is disabled (WUC.APME = 0b). Alternatively, if APM is enabled together with some
of the ACPI/PCIe filters (enabled in the WUFC register), packets matching these filters might wake up
the system even if PCIe PME is disabled.
Parameter Description Min. Max. Notes
t
xog
Xosc stable from power stable 56 ms
t
PE_RST-CLK
PCIe clock valid to PCIe power
good
100 s- According to PCIe spec.
t
PVPGL
Power rails stable to PCIe PE_RST
active
100 ms - According to PCIe spec.
T
pgcfg
External PE_RST signal to first
configuration cycle.
100 ms According to PCIe spec.
t
d0mem
Device programmed from D3h to
D0 state to next device access
10 ms
According to PCI power
management spec.
t
l2pg
L2 link transition to PE_RST de-
assertion
0 ns According to PCIe spec.
t
l2clk
L2 link transition to removal of
PCIe reference clock
100 ns According to PCIe spec.
T
clkpg
PE_RST de-assertion to removal of
PCIe reference clock
0 ns According to PCIe spec.
T
pgdl
PE_RST de-assertion time 100 s According to PCIe spec.
Parameter Description Min. Max. Notes
t
xog
Xosc stable from power stable 56 msec
t
ppg
Internal power good delay from valid power
rail
45 msec
t
ee
NVM read duration 20 msec
t
ppg-clkint
PCIe* PE_RST to internal PLL lock - 5 ms
t
clkpr
Internal PCIe PWGD from external PCIe
PE_RST
50 s
t
pgtrn
PCIe PE_RST to start of link training 20 ms According to PCIe spec.
t
pgres
External PE_RST to response to first
configuration cycle
1 s According to PCIe spec.