Data Sheet

Power Management—Ethernet Controller I210
169
5.5.4 Transition From D0a to Dr and Back Without Transition to D3
Figure 5-6. Transition From D0a to Dr and Back Without Transition to D3
Table 5-5. Transition From D0a to Dr and Back Without Transition to D3
Note Description
1
The system must assert PE_RST_N before stopping the PCIe reference clock. It must also wait t
l2clk
after link transition
to L2/L3 before stopping the reference clock.
2 On assertion of PE_RST_N, the I210 transitions to Dr state and the PCIe link transition to electrical idle.
3 The system starts the PCIe reference clock t
PE_RST-CLK
before de-assertion PE_RST_N.
4 The internal PCIe clock is valid and stable t
ppg-clkint
from PE_RST_N de-assertion.
5 The PCIe internal PWRGD signal is asserted t
clkpr
after the external PE_RST_N signal.
6 Asserting internal PCIe PWRGD causes the Flash to be re-read, asserts PHY reset, and disables wake up.
7 APM wake-up mode might be enabled based on what is read from the Flash.
8 After reading the Flash, PHY reset is de-asserted.
9 Link training starts after t
pgtrn
from PE_RST_N de-assertion.
10 A first PCIe configuration access might arrive after t
pgcfg
from PE_RST_N de-assertion.
11 A first PCI configuration response can be sent after t
pgres
from PE_RST_N de-assertion.
12 Writing a 1b to the Memory Access Enable bit in the PCI Command Register transitions the I210 from D0u to D0 state.
PCIeReferenceClock
PE_RSTn
DState
PHYPowerState
D0u
ReadingFlash ReadFlash
D0a
power‐managed full
ResettoPHY
(activelow)
PCIeLink
WakeUpEnabled
Dr
8
Anymode
APM/SMBus
full
D0a
12
L0 L0
2
3
10
11
1
9
InternalPCIeClock
(2.5GHz)
Internal PwrGd(PLL)
6
4
5
7
tee
tppg‐clkint
tpgtrn
tpgres
tpgcfg
tclkpr
tpgdl
tclkpg
tPWRGD‐CLK