Data Sheet

Ethernet Controller I210 —Power Management
168
5.5.3 Transition From D0a to D3 and Back With PE_RST_N
Figure 5-5. Transition From D0a to D3 and Back With PE_RST_N
Table 5-4. Transition From D0a to D3 and Back With PE_RST_N
Note Description
1 Writing 11b to the Power State field of the PMCSR transitions the I210 to D3. PCIe link transitions to L1 state.
2 The system can delay an arbitrary amount of time between setting D3 mode and moving the link to a L2 or L3 state.
3 Following link transition, PE_RST_N is asserted.
4
The system must assert PE_RST_N before stopping the PCIe reference clock. It must also wait t
l2clk
after link transition
to L2/L3 before stopping the reference clock.
5 On assertion of PE_RST_N, the I210 transitions to Dr state.
6 The system starts the PCIe reference clock t
PE_RST-CLK
before de-assertion PE_RST_N.
7 The internal PCIe clock is valid and stable t
ppg-clkint
from PE_RST_N de-assertion.
8 The PCIe internal PWRGD signal is asserted t
clkpr
after the external PE_RST_N signal.
9 Asserting internal PCIe PWRGD causes the Flash to be re-read, asserts PHY reset, and disables wake up.
10 APM wake-up mode might be enabled based on what is read from the Flash.
11 After reading the Flash, PHY reset is de-asserted.
12 Link training starts after t
pgtrn
from PE_RST_N de-assertion.
13 A first PCIe configuration access might arrive after t
pgcfg
from PE_RST_N de-assertion.
14 A first PCI configuration response can be sent after t
pgres
from PE_RST_N de-assertion.
15 Writing a 1b to the Memory Access Enable bit in the PCI Command Register transitions the I210 from D0u to D0 state.
PCIeReferenceClock
PE_RSTn
DState
PHYPowerState
D0u
ReadingFlash ReadFlash
D0a
power‐managed full
ResettoPHY(active
low)
PCIeLink
WakeUpEnabled
Dr
11
Anymode
APM/SMBus
full
D3write
D0a D3
15
2L1L0L 0L3L/
1
2
6
13
14
3
4a
4b
12
InternalPCIeClock
(2.5GHz)
Internal PwrGd(PLL)
9
7
8
10
tee
tppg‐clkint
tpgtrn
tpgres
tpgcfg
tclkpr
tpgdl
tl2clk
tclkpg
tPWRGD‐CLK
tl2pg
5
L0