Data Sheet

Power Management—Ethernet Controller I210

167

5.5.2 Transition from D0a to D3 and Back Without PE_RST_N

Figure 5-4. Transition from D0a to D3 and Back Without PE_RST_N

Table 5-3. Transition from D0a to D3 and Back Without PE_RST_N

Note Description

Writing 11b to the Power State field of the Power Management Control/Status Register (PMCSR) transitions the I210 to

D3.

2 The system can keep the I210 in D3 state for an arbitrary amount of time.

3 To exit D3 state, the system writes 00b to the Power State field of the PMCSR.

4 APM wake-up or SMBus mode might be enabled based on what is read in the Flash.

After reading the Flash, reset to the PHY is de-asserted. The PHY operates at reduced-speed if APM wake up or SMBus

is enabled, else powered-down.

6 The system can delay an arbitrary time before enabling memory access.

Writing a 1b to the Memory Access Enable bit or to the I/O Access Enable bit in the PCI Command Register transitions

the I210 from D0u to D0 state and returns the PHY to full-power/speed operation.

PCIeReference

Clock

PE_RSTn

PHYReset

PCIeLink

ReadingFlash ReadFlash

DState u0D3D D0

WakeUpEnabled

MemoryAccessEnable

D3write

APM /SMBusAnymode

D0Write

D0a

PHYPowerState

full fulldeganam‐rewopdeganam‐rewop

tee

td0mem