Data Sheet

Ethernet Controller I210 —Power Management
166
5.5.1 Power Up (Off to Dup to D0u to D0a)
Figure 5-3. Power Up (Off to Dup to D0u to D0a)
Table 5-2. Power Up (Off to Dup to D0u to D0a)
Note Description
1 Xosc is stable t
xog
after power is stable.
2 LAN_PWR_GOOD is asserted after all power supplies are good and t
ppg
after Xosc is stable.
3 A Flash read starts on the rising edge of LAN_PWR_GOOD.
4 After reading the Flash, PHY reset is de-asserted.
5 APM wake-up mode can be enabled based on what is read from the Flash.
6 The PCIe reference clock is valid t
PE_RST-CLK
before de-asserting PE_RST_N (according to PCIe specification).
7 PE_RST_N is de-asserted t
PVPGL
after power is stable (according to PCIe specification).
8 The internal PCIe clock is valid and stable t
ppg-clkint
from PE_RST_N de-assertion.
9 The PCIe internal PWRGD signal is asserted t
clkpr
after the external PE_RST_N signal.
10 Asserting internal PCIe PWRGD causes the Flash to be re-read, asserts PHY reset, and disables wake up.
11 After reading the Flash, PHY reset is de-asserted.
12 Link training starts after t
pgtrn
from PE_RST_N de-assertion.
13 A first PCIe configuration access might arrive after t
pgcfg
from PE_RST_N de-assertion.
14 A first PCI configuration response can be sent after t
pgres
from PE_RST_N de-assertion.
15 Writing a 1b to the Memory Access Enable bit in the PCI Command Register transitions the I210 from D0u to D0 state.
InternalPCIeClock
Internal PwrGd(PLL)
DState
D0u
ReadingFlash
D0a
PHYReset
PCIeLinkUp L0
WakeUpEnabled
4
5
7
Dr
10
11
12
3
5
APM/SMBusWakeup
Power
InternalPowerOn
Reset
2
PCIeReferenceClock
PE_RSTn
Read
3GIO
Read
rest
Read
3GIO
Read
rest
Xosc
1
6
8
txog
tee tee
9
tppg‐clkint
13 14
PHYPowerState deganam‐rewoP(FFODD ) DDOFForreducedlinkspeed
On
APM/SMBusWakeup
tpgtrn
15
tpgres
tpgcfg
tPWRGD‐CLK
tPVPG
L
tppg
tclkpr