Data Sheet

Power Management—Ethernet Controller I210
165
• L0s Acceptable Latency (as published in the Endpoint L0s Acceptable Latency field of the Device
Capabilities Register) is loaded from Flash.
The I210 transitions the link into L0s state once the PCIe link has been idle for a period of time defined
in the Latency_To_Enter_L0s field in the CSR Auto Configuration Power-Up NVM section (see
Section 6.3). The I210 will then transition the link into L1 state once the PCIe link has been in L0s state
for a further period as defined in the Latency_To_Enter_L1 field in the CSR Auto Configuration Power-
Up NVM section.
To comply with the PCIe specification, if the link idle time exceeds the Latency_To_Enter_L0s value
defined in the Flash, then the I210 enters L0s.
The following Flash fields control L1 behavior:
• Act_Stat_PM_Sup - Indicates support for ASPM L1 in the PCIe configuration space (loaded into the
Active State Link PM Support field)
• L1_Act_Ext_Latency - Defines L1 active exit latency
• L1_Act_Acc_Latency - Defines L1 active acceptable exit latency
• Latency_To_Enter_L1 - Defines the period (in the L0s state) before the transition into L1 state
5.4.2 Internal PHY Power-Management
The PHY power management features are described in Section 3.7.8.5.
5.4.3 SerDes, SGMII and 1000BASE-KX Power Management
The I210 SerDes enters a power-down state when none of its clients is enabled and therefore has no
need to maintain a link. This can happen in one of the following cases. Note that SerDes and
1000BASE-KX power-down must be enabled through the SerDes Low Power Enable bit in Flash word
0x0F.
1. D3/Dr state: SerDes enters a low-power state if the following conditions are met:
a. The LAN function is in a non-D0 state
b. APM WOL is inactive
c. Pass-through manageability is disabled
d. ACPI PME is disabled
e. The Dynamic Device Off Enable Flash bit is set (word 0x1E.14)
2. PHY mode: SerDes is disabled when its LAN function is configured to PHY mode.
3. Device Off: SerDes can be disabled if the DEV_OFF_N pin is asserted. Since the SerDes is shared
between the LAN function and manageability, it might not be desired to power down the SerDes in
device disable. The PHY_in_LAN_Disable Flash bit (also known as Veto bit) determines whether the
SerDes is powered down when the device disable pin is asserted. The default is not to power down.
5.5 Timing of Power-State Transitions
The following sections give detailed timing for the state transitions. In the diagrams, the dotted
connecting lines represent the I210 requirements, while the solid connecting lines represent the I210
guarantees.
The timing diagrams are not to scale. The clocks edges are shown to indicate running clocks only and
are not to be used to indicate the actual number of cycles for any operation.