Data Sheet

Ethernet Controller I210 —Power Management
164
While in L0 state, the I210 transitions the transmit lane(s) into L0s state once the idle conditions are
met for a period of time as follows:
L0s configuration fields are:
• L0s enable - The default value of the Active State Link PM Control field in the PCIe Link Control
Register is set to 00b (both L0s and L1 disabled). System software might later write a different
value into the Link Control register. The default value is loaded on any reset of the PCI configuration
registers.
• L0s exit latency (as published in the L0s Exit Latency field of the Link Capabilities register) is loaded
from Flash. Separate values are loaded when the I210 shares the same reference PCIe clock with
its partner across the link, and when the I210 uses a different reference clock than its partner
across the link. The I210 reports whether it uses the slot clock configuration through the PCIe Slot
Clock Configuration bit loaded from the Slot_Clock_Cfg bit in the PCIe Init Configuration 3 Flash
Word.
Figure 5-2. Link Power Management State Diagram
L3
L1
PERST# de-
assertion
PERST#
assertion
PERST#
assertion
PERST#
assertion
Write 11b
to Power State
Write 00b
to Power State
& (BME = 0 OR
No_Soft_Reset = 0)
Enable
master access
Internal Power On
Reset assertion
L2
L0
L0s
L1
Dr
D0u
L0
L0s
L1
D0a
D3
Write 11b
to Power State
Write 00b to Power State
& No_Soft_Reset = 1
& BME = 1