Data Sheet
Power Management—Ethernet Controller I210
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The I210 exceeds the allocated auxiliary power in some configurations. The I210 must therefore be
configured to meet the previously mentioned requirements. To do so, the I210 implements three Flash
bits to disable operation in certain cases:
1. The PHPM.Disable_1000 PHY register bit disables 1000 Mb/s operation under all conditions.
2. The PHPM.Disable 1000 in non-D0a PHY CSR bit disables 1000 Mb/s operation in non-D0a states
1
.
If PHPM.Disable 1000 in non-D0a is set, and the I210 is at 1000 Mb/s speed on entry to a non-D0a
state, then the I210 removes advertisement for 1000 Mb/s and auto-negotiates.
3. The PHPM.Disable 100 in non-D0a PHY CSR bit disables 1000 Mb/s and 100 Mb/s operation in non-
D0a states. If PHPM.Disable 100 in non-D0a is set, and the I210 is at 1000 Mb/s or 100 Mb/s
speeds on entry to a non-D0a state, then the I210 removes advertisement for 1000 Mb/s and 100
Mb/s and auto-negotiates.
Note that the I210 restarts link auto-negotiation each time it transitions from a state where
1000 Mb/s or 100 Mb/s speed is enabled to a state where 1000 Mb/s or 100 Mb/s speed is disabled, or
vice versa. For example, if PHPM.Disable 1000 in non-D0a is set but PHPM.Disable_1000 is cleared, the
I210 restarts link auto-negotiation on transition from D0 state to D3 or Dr states.
5.4 Interconnects Power Management
This section describes the power reduction techniques employed by the I210 main interconnects.
5.4.1 PCIe Link Power Management
The I210 supports all PCIe power management link states:
• L0 state is used in D0u and D0a states.
• The L0s state is used in D0a and D0u states each time link conditions apply.
• The L1 state is also used in D0a and D0u states when idle conditions apply for a longer period of
time. The L1 state is also used in the D3 state.
• The L2 state is used in the Dr state following a transition from a D3 state if PCI-PM PME is enabled.
• The L3 state is used in the Dr state following power up, on transition from D0a, and if PME is not
enabled in other Dr transitions.
The I210 support for active state link power management is reported via the PCIe Active State Link PM
Support register and is loaded from the Flash.
1. The restriction is defined for all non-D0a states to have compatible behavior with previous
products.