Data Sheet

Power Management—Ethernet Controller I210
161
Once the I210 enters Dr state on power-up, the Flash is read. If the Flash contents determine that the
conditions to enter Dr disable mode are met, the I210 then enters this mode (assuming that PCIe
PE_RST_N is still asserted).
The I210 exits Dr disable mode when Dr state is exited (See Figure 5-1 for conditions to exit Dr state).
Refer to Section 5.2.6 for details about the static/dynamic device off states built on Dr Disable Mode.
5.2.4.2 Entry to Dr State
Dr entry on platform power-up begins with the assertion of the internal power detection circuit. The
Flash is read and determines the I210 configuration. If the APM Enable bit in the Flash's Initialization
Control Word 3 is set, then APM wake up is enabled. PHY and MAC states are redetermined by the state
of manageability and APM wake. To reduce power consumption, if manageability or APM wake is
enabled, the PHY auto-negotiates to a lower link speed on Dr entry (See Section 3.7.8.5.4). The PCIe
link is not enabled in Dr state following system power up (since PE_RST_N is asserted).
Entering Dr state from D0a state is done by asserting PE_RST_N. An ACPI transition to the G2/S5 state
is reflected in the I210 transition from D0a to Dr state. The transition can be orderly (such as user
selecting the shut down option), in which case the software device driver might have a chance to
intervene. Or, it might be an emergency transition (such as power button override), in which case, the
software device driver is not notified.
To reduce power consumption, if any of manageability, APM wake or PCI-PM PME
1
is enabled, the PHY
auto-negotiates to a lower link speed on D0a to Dr transition (see Section 3.7.8.5.4).
Transition from D3 (hot) state to Dr state is done by asserting PE_RST_N. Prior to that, the system
initiates a transition of the PCIe link from L1 state to either the L2 or L3 state (assuming all functions
were already in D3 state). The link enters L2 state if PCI-PM PME is enabled.
5.2.4.3 Auxiliary Power Usage
The Flash D3COLD_WAKEUP_ADVEN bit and the AUX_PWR strapping pin determine when D3cold PME is
supported:
• D3COLD_WAKEUP_ADVEN denotes that PME wake should be supported
• AUX_PWR strapping pin indicates that auxiliary power is provided
D3cold PME is supported as follows:
•If the D3COLD_WAKEUP_ADVEN is set to 1b and the AUX_PWR strapping is set to 1b, then D3cold
PME is supported
•Else D3cold PME is not supported
The amount of power required for the function (including the entire NIC) is advertised in the Power
Management Data register, which is loaded from the Flash.
If D3cold is supported, the PME_En and PME_Status bits of the PMCSR, as well as their shadow bits in
the Wake Up Control (WUC) register are reset only by the power-up reset (detection of power rising).
1. ACPI 2.0 specifies that “OSPM will not disable wake events before setting the SLP_EN bit when
entering the S5 sleeping state. This provides support for remote management initiatives by
enabling Remote Power On (RPO) capability. This is a change from ACPI 1.0 behavior.”