Data Sheet

Power Management—Ethernet Controller I210
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In order to reduce power consumption, if the link is still needed for manageability, wake-up or proxying
functionality, the PHY can auto-negotiate to a lower link speed on D3 entry (See Section 3.7.8.5.4).
5.2.3.2 Exit from D3 State
A D3 state is followed by either a D0u state (in preparation for a D0a state) or by a transition to Dr
state (PCI-PM D3cold state). To transition back to D0u, the system writes a 00b to the Power State field
of the Power Management Control/Status Register (PMCSR). Transition to Dr state is through
PE_RST_N assertion.
The No_Soft_Reset bit in the PMCSR register in the I210 is set to 1b, to indicate that the I210 does not
perform an internal reset on transition from D3hot to D0 so that transition does not disrupt the proper
operation of other active functions. In this case, software is not required to re-initialize the function’s
configuration space after a transition from D3hot to D0 (the function is in the D0
initialized
state);
however, the software device driver needs to re-initialize internal registers since transition from D3hot
to D0 causes an internal port reset (similar to asserting the CTRL.RST bit).
The I210 can also be configured via Flash to clear the No_Soft_Reset bit in the PMCSR register (see
Section 6.2.17). In this case, an internal reset is generated when transition from D3hot to D0 occurs
and functional context is not maintained also in PCIe configuration bits (except for bits defined as
sticky). In this case, software is required to fully re-initialize the function after a transition to D0 as the
Function is in the D0
uninitialized
state.
Note: The function is reset if the link state has made a transition to the L2/L3 ready state, on
transition from D3cold to D0, if FLR is asserted or if transition D3hot to D0 is caused by
assertion of PCIe reset (PE_RST pin) regardless of the value of the No_Soft_Reset bit.
5.2.3.3 Master Disable Via CTRL Register
System software can disable master accesses on the PCIe link by either clearing the PCI Bus Master bit
or by bringing the function into a D3 state. From that time on, the I210 must not issue master
accesses. Due to the full-duplex nature of PCIe, and the pipelined design in the I210, it might happen
that multiple requests are pending when the master disable request arrives. The protocol described in
this section insures that a function does not issue master requests to the PCIe link after its Master
Enable bit is cleared (or after entry to D3 state).
Two configuration bits are provided for the handshake between the I210 function and its software
device driver:
• GIO Master Disable bit in the Device Control (CTRL) register - When the GIO Master Disable bit is
set, the I210 blocks new master requests by this function. the I210 then proceeds to issue any
pending requests by this function. This bit is cleared on master reset (LAN_PWR_GOOD, PCIe reset
and software reset) to enable master accesses.
• GIO Master Enable Status bit in the Device Status (STATUS) register - Cleared by the I210 when
the GIO Master Disable bit is set and no master requests are pending and is set otherwise.
Indicates that no master requests are issued by this function as long as the GIO Master Disable bit
is set. The following activities must end before the I210 clears the GIO Master Enable Status bit:
— Master requests by the transmit and receive engines (for both data and MSI/MSI-X interrupts).
— All pending completions to the I210 are received.