Data Sheet

Ethernet Controller I210 —Power Management
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5.2.3 D3 State (PCI-PM D3hot)
The I210 transitions to D3 when the system writes a 11b to the Power State field of the Power
Management Control/Status Register (PMCSR). Any wake-up filter settings that were enabled before
entering this state are maintained. If the PMCSR.No_Soft_reset bit is cleared upon completion or during
the transition to D3 state, the I210 clears the Memory Access Enable and I/O Access Enable bits of the
PCI Command register, which disables memory access decode. If the PMCSR.No_Soft_reset bit is set
the I210 doesn’t clear any bit in the PCIe configuration space. While in D3, the I210 does not generate
master cycles.
Configuration and message requests are the only TLPs accepted by a function in the D3hot state. All
other received requests must be handled as unsupported requests, and all received completions are
handled as unexpected completions. If an error caused by a received TLP (such as an unsupported
request) is detected while in D3hot, and reporting is enabled, the link must be returned to L0 if it is not
already in L0 and an error message must be sent. See section 5.3.1.4.1 in The PCIe Base Specification.
5.2.3.1 Entry to D3 State
Transition to D3 state is through a configuration write to the Power State field of the PMCSR PCIe
configuration register.
Prior to transition from D0 to the D3 state, the software device driver disables scheduling of further
tasks to the I210; it masks all interrupts and does not write to the Transmit Descriptor Tail (TDT)
register or to the Receive Descriptor Tail (RDT) register and operates the master disable algorithm as
defined in Section 5.2.3.3.
If wake up capability is needed, the system should enable wake capability by setting to 1b the PME_En
bit in the PMCSR PCIe configuration register. After wake capability has been enabled, the software
device driver should set up the appropriate wake up registers (WUC, WUFC and associated filters) prior
to the D3 transition.
Note: The software device driver can override the PMCSR.PME_En bit setting via the WUC.APMPME
bit.
If Protocol offload (Proxying) capability is required and the MANC.MPROXYE bit is set to 1b,the software
device driver should:
1. Send to the firmware the relevant protocol offload information (type of protocol offloads required,
MAC and IPv4/6 addresses information for protocol offload) via the shared RAM Firmware/Software
Host interface as defined in Section 8.23.1, Section 10.8 and Section 10.8.2.3.
2. Program the PROXYFC register and associated filters according to the protocol offload required.
3. Program the WUC.PPROXYE bit to 1b.
Note: If operation during D3
cold
is required, even when wake capability is not required (such as for
manageability operation), the system should also set the Auxiliary (AUX) Power PM Enable bit
in the PCIe Device Control register.
As a response to being programmed into D3 state, the I210 transitions its PCIe link into the L1 link
state. As part of the transition into L1 state, the I210 suspends scheduling of new TLPs and waits for
the completion of all previous TLPs it has sent. If the PMCSR.No_Soft_reset bit is cleared, the I210
clears the Memory Access Enable and I/O Access Enable bits of the PCI Command register, which
disables memory access decode. Any receive packets that have not been transferred into system
memory are kept in the I210 (and discarded later on D3 exit). Any transmit packets that have not been
sent can still be transmitted (assuming the Ethernet link is up).