Data Sheet

Power Management—Ethernet Controller I210
157
5.2.1 D0 Uninitialized State (D0u)
The D0u state is an architectural low-power state.
When entering D0u, the I210:
• Asserts a reset to the PHY while the Flash is being read.
• Disables wake up. However APM wake up is enabled (See additional information in Section 5.6.1), if
all of the following register bits are set:
—The WUC.APME bit is set to 1b.
—The WUC.APMPME bit or the PMCSR.PME_en bits are set to 1b.
—The WUC.EN_APM_D0 bit is set to 1b.
5.2.1.1 Entry into D0u state
D0u is reached from either the Dr state (on de-assertion of PE_RST_N) or the D3hot state (by
configuration software writing a value of 00b to the Power State field of the PCI PM registers).
De-asserting PE_RST_N means that the entire state of the I210 is cleared, other than sticky bits. State
is loaded from the Flash, followed by establishment of the PCIe link. Once this is done, configuration
software can access the I210.
On a transition from D3hot state to D0u state, the I210 PCI configuration space is not reset (since the
No_Soft_Reset bit in the PMCSR register is set to 1b). However following move to D0a state, the I210
requires that the software device driver perform a full re-initialization of the function.
5.2.2 D0active State
Once memory space is enabled, the I210 enters the D0 active state. It can transmit and receive
packets if properly configured by the software device driver. The PHY is enabled or re-enabled by the
software device driver to operate/auto-negotiate to full line speed/power if not already operating at full
capability.
Notes:
1. In the I210, if the WUC.EN_APM_D0 is cleared to 0b an APM wake event due to reception of a Magic
packet is not generated when the function is not in D3 (or Dr) state. Any APM wake up previously
active remains active when moving from D3 to D0.
2. If APM wake is required in D3 software device driver should not disable APM wake-up via the
WUC.APME bit on D0 entry. Otherwise APM wake following a system crash and entry into S3, S4 or
S5 system power management state is not enabled.
3. Following entry into D0,the software device driver can activate other wake-up filters by writing to
the Wake Up Filter Control (WUFC) register.
5.2.2.1 Entry to D0a State
D0a is entered from the D0u state by writing a 1b to the Memory Access Enable or the I/O Access
Enable bit of the PCI Command register (See Section 9.3.3). The DMA, MAC, and PHY of the
appropriate LAN function are also enabled.