Data Sheet

Ethernet Controller I210 —Power Management
156
• L2/L3 Ready: This link state prepares the PCIe link for the removal of power and clock. The I210 is
in the D3hot state and is preparing to enter D3cold. The power-saving opportunities for this state
include, but are not limited to, clock gating of all PCIe architecture logic, shutdown of the PLL, and
shutdown of all transceiver circuitry.
• L2: This link state is intended to comprehend D3cold with auxiliary power support. Note that
sideband PE_WAKE_N signaling exists to cause wake-capable devices to exit this state. The power-
saving opportunities for this state include, but are not limited to, shutdown of all transceiver
circuitry except detection circuitry to support exit, clock gating of all PCIe logic, and shutdown of
the PLL as well as appropriate platform voltage and clock generators.
• L3 (link off): Power and clock are removed in this link state, and there is no auxiliary power
available. To bring the I210 and its link back up, the platform must go through a boot sequence
where power, clock, and reset are reapplied appropriately.
5.2 Power States
The I210 supports the D0 and D3 architectural power states as described earlier. Internally, the I210
supports the following power states:
• D0u (D0 un-initialized) - an architectural sub-state of D0
• D0a (D0 active) - an architectural sub-state of D0
• D3 - architecture state D3hot
• Dr - internal state that contains the architecture D3cold state. Dr state is entered when PE_RST_N
is asserted or a PCIe in-band reset is received
Figure 5-1 shows the power states and transitions between them.
Figure 5-1. Power Management State Diagram
Dr D0u
D0aD3
PERST# de- assertion
& Flash read done
PERST# assertion
PERST#
assertion
PERST#
assertion
Write 11b
to Power State
Write 00b
to Power State
Enable
master or slave
access
Internal Pow er On
Reset assertion
Hot (in-band)
Reset
Write 11b
to Power State