Data Sheet

Power Management—Ethernet Controller I210
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5.0 Power Management
This section describes how power management is implemented in the I210. The I210 supports the
Advanced Configuration and Power Interface (ACPI) specification as well as Advanced Power
Management (APM).
Power management can be disabled via the power management bit in the Initialization Control Word 1
Flash word (see Section 6.2.2), which is loaded during power-up reset. Even when disabled, the power
management register set is still present. Power management support is required by the PCIe
specification.
5.1 General Power State Information
5.1.1 PCI Device Power States
The PCIe Specification defines function power states (D-states) that enable the platform to establish
and control power states for the I210 ranging from fully on to fully off (drawing no power) and various
in-between levels of power-saving states, annotated as D0-D3. Similarly, PCIe defines a series of link
power states (L-states) that work specifically within the link layer between the I210 and its upstream
PCIe port (typically in the host chipset).
For a given device D-state, only certain L-states are possible as follows.
• D0 (fully on): The I210 is completely active and responsive during this D-state. The link can be in
either L0 or a low-latency idle state referred to as L0s. Minimizing L0s exit latency is paramount for
enabling frequent entry into L0s while facilitating performance needs via a fast exit. A deeper link
power state, L1 state, is supported as well.
• D1 and D2: These modes are not supported by the I210.
• D3 (off): Two sub-states of D3 are supported:
— D3hot, where primary power is maintained.
— D3cold, where primary power is removed.
Link states are mapped into device states as follows:
— D3hot maps to L1 to support clock removal on mobile platforms
— D3cold maps to L2 if auxiliary power is supported on the I210 with wake-capable logic, or to L3
if no power is delivered to the I210. A sideband PE_WAKE_N mechanism is supported to
interface wake-enabled logic on mobile platforms during the L2 state.
5.1.2 PCIe Link Power States
Table 5-1 lists allowable mapping from D-states to L-states on the PCIe link.
Configuring the I210 into a D-state automatically causes the PCIe link to transition to the appropriate
L-state.