Data Sheet

Ethernet Controller I210 —Initialization
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4.5.8 Initialization of Statistics
Statistics registers are hardware-initialized to values as detailed in each particular register's
description. The initialization of these registers begins upon transition to D0active power state (when
internal registers become accessible, as enabled by setting the Memory Access Enable bit of the PCIe
Command register), and is guaranteed to be completed within 1 s of this transition. Access to
statistics registers prior to this interval might return indeterminate values.
All of the statistical counters are cleared on read and a typical device driver reads them (thus making
them zero) as a part of the initialization sequence.
4.5.9 Receive Initialization
Program the receive address register(s) per the station address. This can come from the Flash or by
any other means (for example, on some machines, this comes from the system PROM not the Flash on
the adapter card).
Set up the Multicast Table Array (MTA) by software. This means zeroing all entries initially and adding
in entries as requested.
Program the RXPBSIZE register so that the total size formed by the receive packet buffer plus the BMC
to OS buffer plus the transmit packet buffer(s) plus the OS to BMC buffer does not exceed 60 KB:
RXPBSIZE.Rxpbsize + RXPBSIZE.Bmc2ospbsize + TXPBSIZE.Txpb0size + TXPBSIZE.Txpb1size +
TXPBSIZE.Txpb2size + TXPBSIZE.Txpb3size + TXPBSIZE.os2Bmcpbsize <= 60 KB
Program RCTL with appropriate values. If initializing it at this stage, it is best to leave the receive logic
disabled (RCTL.RXEN = 0b) until after the receive descriptor rings have been initialized. If VLANs are
not used, software should clear VFE. Then there is no need to initialize the VFTA. Select the receive
descriptor type.
The following should be done once per receive queue needed:
1. Allocate a region of memory for the receive descriptor list.
2. Receive buffers of appropriate size should be allocated and pointers to these buffers should be
stored in the descriptor ring.
3. Program the descriptor base address with the address of the region.
4. Set the length register to the size of the descriptor ring.
5. Program SRRCTL of the queue according to the size of the buffers, the required header handling
and the drop policy.
6. If header split or header replication is required for this queue, program the PSRTYPE register
according to the required headers.
7. Enable the queue by setting RXDCTL.ENABLE. In the case of queue zero, the enable bit is set by
default - so the ring parameters should be set before RCTL.RXEN is set.
8. Poll the RXDCTL register until the ENABLE bit is set. The tail should not be bumped before this bit
was read as one.
9. Program the direction of packets to this queue according to the mode selected in the MRQC register.
Packets directed to a disabled queue are dropped.
Note: The tail register of the queue (RDT[n]) should not be bumped until the queue is enabled.