Data Sheet
Ethernet Controller I210 —Initialization
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4.4.4 BIOS Handling of Device Disable
4.4.4.1 Sequence for Entering the (Static) Device Off State
1. BIOS recognizes that the entire device should be disabled. The Device Off Enable Flash bit in word
0x1E should be set to 1b.
a. In order to shut down the PHY together with the rest of the device, the PHY_in_LAN_Disable
Flash bit (refer to Section 6.2.21) should be set to 1b.
2. BIOS asserts the DEV_OFF_N pin (device is on and not in PCIe reset).
3. BIOS issues a PCIe reset
4. PCIe reset sequence ends while the device is already in off state (minimum PCIe reset duration is
100 s).
5. The BIOS places the Link in the Electrical IDLE state (at the other end of the PCIe link) by clearing
the LINK Disable bit in the Link Control register.
6. BIOS might start with the device enumeration procedure (the I210 device function is now invisible).
7. Proceed with normal operation.
4.4.4.2 Sequence for Returning from the (Static) Device Off State
1. Device is in its off state.
2. BIOS de-asserts the DEV_OFF_N pin (while device is off but not while in PCIe reset)
3. BIOS issues a PCIe reset.
4. PCIe reset sequence ends while the device is already in on state (PCIe interface must be operative
within 100 ms).
5. BIOS might start with the device enumeration procedure (the I210 device function is now visible).
6. Proceed with normal operation.
4.5 Software Initialization and Diagnostics
4.5.1 Introduction
This section discusses general software notes for the I210, especially initialization steps. This includes
general hardware, power-up state, basic device configuration, initialization of transmit and receive
operation, link configuration, software reset capability, statistics, and diagnostic hints.
4.5.2 Power Up State
When the I210 powers up it reads the Flash. The Flash contains sufficient information to bring the link
up and configure the I210 for manageability and/or APM wakeup. However, software initialization is
required for normal operation.
The power-up sequence, as well as transitions between power states, are described in Section 4.1.1.
The detailed timing is given in Section 5.5. The next section gives more details on configuration
requirements.