Data Sheet

Ethernet Controller I210 —Initialization
142
a. The Tx packet buffers
b. The Rx packet buffers
14. Includes EEC.REQ, EEC.GNT, FLA.REQ and FLA.GNT fields.
15. The following DMA registers are cleared only by LAN_PWR_GOOD, PCIe Reset or CTRL.DEV_RST:
DMCTLX, DTPARS, DRPARS and DDPARS.
16. CTRL.DEV_RST assertion causes read of function related sections.
4.3.3 PHY Behavior During a Manageability Session
During some manageability sessions (such as an IDER or SoL session as initiated by an external MC),
the platform is reset so that it boots from a remote media. This reset must not cause the Ethernet link
to drop since the manageability session is lost. Also, the Ethernet link should be kept on continuously
during the session for the same reasons. The I210 therefore limits the cases in which the internal PHY
would restart the link, by masking two types of events from the internal PHY:
• PE_RST# and PCIe resets (in-band and link drop) do not reset the PHY during such a manageability
session
• The PHY does not change link speed as a result of a change in power management state, to avoid
link loss. For example, the transition to D3hot state is not propagated to the PHY.
— Note however that if main power is removed, the PHY is allowed to react to the change in power
state (the PHY might respond in link speed change). The motivation for this exception is to
reduce power when operating on auxiliary power by reducing link speed.
The capability described in this section is disabled by default on LAN_POWER_GOOD reset. The
Keep_PHY_Link_Up_En bit in the Flash must be set to 1b to enable it. Once enabled, the feature is
enabled until the next LAN_POWER_GOOD (the I210 does not revert to the hardware default value on
PE_RST#, PCIe reset or any other reset but LAN_POWER_GOOD).
When the Keep_PHY_Link_Up bit (also known as Veto bit) in the MANC register is set, the following
behaviors are disabled:
• The PHY is not reset on PE_RST# and PCIe resets (in-band and link drop). Other reset events are
not affected - LAN_POWER_GOOD reset, Device Disable, Force TCO, and PHY reset by software.
• The PHY does not change its power state. As a result link speed does not change.
• The I210 does not initiate configuration of the PHY to avoid losing link.
The Keep_PHY_Link_Up bit is set by the MC through the Management Control command (refer to
Section 10.5.9.1.5 for SMBus command and Section 10.6.3.10 for NC-SI command) on the sideband
interface. It is cleared by the external MC (again, through a command on the sideband interface) when
the manageability session ends. Once the Keep_PHY_Link_Up bit is cleared, the PHY updates its Dx
state and acts accordingly (negotiates its speed).
The Keep_PHY_Link_Up bit is a read/write bit and can be accessed by host software, but software is not
expected to clear the bit. The bit is cleared in the following cases:
• On LAN_POWER_GOOD.
• When the MC resets or initializes it.