Data Sheet

Ethernet Controller I210 —Initialization
140
Notes:
1. If AUX_POWER = 0b the Wakeup Context is reset (PME_Status and PME_En bits should be 0b at
reset if the I210 does not support PME from D3cold).
2. The MMS unit must configure the PHY after any PHY reset.
3. The following register fields do not follow the general rules previously described:
a. CTRL.SDP0_IODIR, CTRL.SDP1_IODIR, CTRL_EXT.SDP2_IODIR, CTRL_EXT.SDP3_IODIR,
CONNSW.ENRGSRC field, CTRL_EXT.SFP_Enable, CTRL_EXT.LINK_MODE, CTRL_EXT.EXT_VLAN
and LED configuration registers are reset on LAN_PWR_GOOD only. Any Flash read resets these
fields to the values in the Flash.
b. The Aux Power Detected bit in the PCIe Device Status register is reset on LAN_PWR_GOOD and
PE_RST_N (PCIe reset) assertion only.
c. FLA - reset on LAN_PWR_GOOD only.
d. The bits mentioned in the next note.
4. The following registers are part of this group:
a. VPD registers
b. Max payload size field in PCIe Capability Control register (offset 0xA8).
c. Active State Link PM Control field, Common Clock Configuration field and Extended Synch field
in PCIe Capability Link Control register (Offset 0xB0).
d. Read Completion Boundary in the PCIe Link Control register (Offset 0xB0).
5. The following registers are part of this group:
a. SWSM
b. GCR (only part of the bits - see register description for details)
c. FUNCTAG
d. GSCL_1/2/3/4
e. GSCN_0/1/2/3
f. SW_FW_SYNC - only part of the bits - see register description for details.
6. The following registers are part of this group:
a. MSIX control register, MSIX PBA and MSIX per vector mask.
7. The Wake Up Context is defined in the PCI Bus Power Management Interface Specification (sticky
bits). It includes:
— PME_En bit of the Power Management Control/Status Register (PMCSR).
— PME_Status bit of the Power Management Control/Status Register (PMCSR).
— Aux_En in the PCIe registers
— The device Requester ID (since it is required for the PM_PME TLP).
Flash Request X X 14.
PHY/SerDes PHY X X X X 2.
Strapping Pins
Table 4-3. I210 Reset Affects - Other Resets (Continued)
Reset Activation D3hotD0 FLR
Port SW
Reset
(CTRL.RST)
Force
TCO
EE
Reset
PHY
Reset
Notes