Data Sheet

Initialization—Ethernet Controller I210
137
4.3.1.2 Force TCO
This reset is generated when manageability logic is enabled and the MC detects that the I210 does not
receive or transmit data correctly. Force TCO reset is enabled if the Reset on Force TCO bit in the
Management Control Flash word is set 1b. Table 4-3 describes affects of TCO reset on the I210
functionality.
Force TCO reset is generated in pass through mode when the MC issues a Force TCO command with bit
1 set and the previous conditions exist.
4.3.1.3 Flash Reset
Writing a 1b to the Flash Reset bit of the Extended Device Control Register (CTRL_EXT.EE_RST) causes
the I210 to re-read the per-function configuration from the Flash, setting the appropriate bits in the
registers loaded by the Flash.
4.3.1.4 PHY Reset
Software can write a 1b to the PHY Reset bit of the Device Control Register (CTRL.PHY_RST) to reset
the internal PHY. The PHY is internally configured after a PHY reset.
Note: The internal PHY should not be reset using PHYREG 0,0 bit 15 (Copper Control
Register.Copper Reset), since in this case, the internal PHY configuration process is bypassed
and there is no guarantee the PHY operates correctly.
Because the PHY can be accessed by the internal firmware and software device driver software, the
software device driver software should coordinate any PHY reset with the firmware using the following
procedure:
1. Check that MANC.BLK_Phy_Rst_On_IDE (offset 0x5820 bit 18) is cleared. If set, the MC requires a
stable link and thus the PHY should not be reset at this stage. The software device driver might skip
the PHY reset if not mandatory or wait for MANC.BLK_Phy_Rst_On_IDE to clear. Refer to
Section 4.3.3 for more details.
2. Take ownership of the PHY using the following flow:
a. Get ownership of the software/firmware semaphore SWSM.SWESMBI bit (offset 0x5B50 bit 1):
•Set the SWSM.SWESMBI bit.
•Read SWSM.
•If SWSM.SWESMBI was successfully set (semaphore was acquired); otherwise, go back to
step a.
• This step assures that the internal firmware does not access the shared resources register
(SW_FW_SYNC).
b. Software reads the Software-Firmware Synchronization Register (SW_FW_SYNC) and checks the
bit that controls the PHY it wants to own.
• If the bit is set (firmware owns the PHY), software tries again later.
c. Release ownership of the software/firmware semaphore by clearing the SWSM.SWESMBI bit.
3. Drive the PHY reset bit in CTRL bit 31.
4. Wait 100 s.
5. Release PHY reset in CTRL bit 31.
6. Release ownership of the relevant PHY to firmware using the following flow:
a. Get ownership of the software/firmware semaphore SWSM.SWESMBI (offset 0x5B50 bit 1):