Data Sheet

Ethernet Controller I210 —Initialization
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A FLR reset to a function resets all the queues, interrupts, and statistics registers attached to the
function. It also resets PCIe read/write configuration bits as well as disables transmit and receive flows
for the queues allocated to the function. All pending read requests are dropped and PCIe read
completions to the function might be completed as unexpected completions and silently discarded
(following update of flow control credits) without logging or signaling as an error.
Note: If software initiates a FLR when the Transactions Pending bit in the Device Status
configuration register is set to 1b (refer to Section 9.4.6.6), then software must not initialize
the function until allowing time for any associated completions to arrive. The Transactions
Pending bit is cleared upon completion of the FLR.
4.3 Software Reset
4.3.1 Software Reset (RST)
Software can reset the I210 by setting the Software Reset (CTRL.RST) bit in the Device Control
register. Following reset, the PCI configuration space (configuration and mapping) of the device is
unaffected. Prior to issuing a software reset the software device driver needs to operate the master
disable algorithm as defined in Section 5.2.3.3.
The CTRL.RST bit is provided primarily to recover from an indeterminate or suspected port hung
hardware state. Most registers (receive, transmit, interrupt, statistics, etc.) and state machines in the
port are set to their power-on reset values, approximating the state following a power-on or PCIe reset
(refer to Table 4-3 for further information on affects of software reset). However, PCIe configuration
registers and DMA logic is not reset, leaving the device mapped into system memory space and
accessible by a software device driver.
Note: To ensure that a software reset fully completed and that the I210 responds correctly to
subsequent accesses after setting the CTRL.RST bit, the software device driver should wait at
least 3 ms before accessing any register and then verify that EEC.Auto_RD is set to 1b and
that the STATUS.PF_RST_DONE bit is set to 1b.
When asserting the CTRL.RST software reset bit, only some Flash bits related to the specific function
are re-read (refer to Section 3.3.1.2). Bits re-read from Flash are reset to default values.
4.3.1.1 Bus Master Enable (BME)
Disabling bus master activity of a function by clearing the Configuration Command register.BME bit to
0b, resets all DMA activities and MSI/MSIx operations related to the port. The master disable resets
only the DMA activities related to this function without affecting activity of other functions or LAN ports.
Configuration accesses and target accesses to the function are still enabled and the Management
Controller (MC) can still transmit and receive packets on the port.
A Master Disable resets all the queues and DMA related interrupts. It also disables the transmit and
receive flows. All pending read requests are dropped and PCIe read completions to this function might
be completed as unexpected completions and silently discarded (following update of flow control
credits) without logging or signaling it as an error.
Note: Prior to issuing a master disable the software device driver needs to implement the master
disable algorithm as defined in Section 5.2.3.3. After Master Enable is set back to 1b,the
software device driver should re-initialize the transmit and receive queues.