Data Sheet

Initialization—Ethernet Controller I210
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4.2.1 Reset Sources
The I210 reset sources are described in the sections that follow.
4.2.1.1 LAN_PWR_GOOD
The I210 has an internal mechanism for sensing the power pins. Once power is up and stable, the I210
creates an internal reset. This reset acts as a master reset of the entire chip. It is level sensitive, and
while it is zero holds all of the registers in reset. LAN_PWR_GOOD is interpreted to be an indication that
device power supplies are all stable. Note that LAN_PWR_GOOD changes state during system power-
up.
4.2.1.2 PE_RST_N
De-asserting PE_RST_N indicates that both the power and the PCIe clock sources are stable. This pin
asserts an internal reset also after a D3cold exit. Most units are reset on the rising edge of PE_RST_N.
The only exception is the PCIe unit, which is kept in reset while PE_RST_N is asserted (level).
4.2.1.3 In-Band PCIe Reset
The I210 generates an internal reset in response to a physical layer message from the PCIe or when
the PCIe link goes down (entry to polling or detect state). This reset is equivalent to PCI reset in
previous (PCI) GbE LAN controllers.
4.2.1.4 D3hot to D0 Transition
This is also known as ACPI reset. The I210 generates an internal reset on the transition from D3hot
power state to D0 (caused after configuration writes from D3 to D0 power state).
When the PMCSR.No_Soft_Reset bit in the configuration space is set, on transition from D3hot to D0
the I210 resets internal CSRs (similar to CTRL.RST assertion) but doesn’t reset registers in the PCIe
configuration space. If the PMCSR.No_Soft_Reset bit is cleared, the I210 resets all per-function
registers except for registers defined as sticky in the configuration space.
Note: Regardless of the value of the PMCSR.No_Soft_Reset bit, the function is reset (including bits
that are not defined as sticky in PCIe configuration space) if the link state has transitioned to
the L2/L3 ready state, on transition from D3cold to D0, if Function Level Reset (FLR) is
asserted or if transition D3hot to D0 is caused by asserting the PCIe reset (PE_RST pin).
Note: Software device drivers should implement the handshake mechanism defined in
Section 5.2.3.3 to verify that all pending PCIe completions finish, before moving the I210 to
D3.
4.2.1.5 FLR
A FLR function reset is issued by setting bit 15 in the Device Control configuration register (refer to
Section 9.4.6.5), which is equivalent to a D0  D3  D0 transition. The only difference is that this reset
does not require software device driver intervention in order to stop the master transactions of this
function. The Flash content is partially reloaded after a FLR reset. The words read from Flash at FLR are
the same as read following a full software reset. A list of these words can be found in Section 3.3.1.2.