Data Sheet

Ethernet Controller I210 —Initialization
134
4.1.2 Power-Up Timing Diagram
4.2 Reset Operation
The I210 has a number of reset sources described in the sections that follow. After a reset, the software
device driver should verify that the EEMNGCTL.CFG_DONE bit (refer to Section 8.4.18) is set to 1b and
no errors were reported in the FWSM.Ext_Err_Ind (refer to Section 8.7.2) field.
Figure 4-2. Power-Up Timing Diagram
Table 4-1. Notes to Power-Up Timing Diagram
Note
1 Xosc is stable t
xog
after the Power is stable
2 Internal Reset is released after all power supplies are good and t
ppg
after Xosc is stable.
3 A Flash read starts on the rising edge of the internal Reset or LAN_PWR_GOOD.
4 After reading the Flash, the PHY might exit power down mode.
5 APM Wakeup and/or manageability might be enabled based on Flash contents.
6 The PCIe reference clock is valid t
PE_RST-CLK
before the de-assertion of PE_RST# (according to PCIe specification).
7PE_RST# is de-asserted t
PVPGL
after power is stable (according to PCIe specification).
8
De-assertion of PE_RST# causes the Flash to be re-read, asserts PHY power-down (except if the Veto bit also known as
Keep_PHY_Link_Up bit is set), and disables Wake Up.
9 After reading the Flash, the PHY exits power-down mode.
10 Link training starts after t
pgtrn
from PE_RST# de-assertion.
11 A first PCIe configuration access might arrive after t
pgcfg
from PE_RST# de-assertion.
12 A first PCI configuration response can be sent after tpgres from PE_RST# de-assertion
13 Writing a 1b to the Memory Access Enable bit in the PCI Command Register transitions the device from D0u to D0 state.
D‐State D0u
FlashLoad
D0a
PHYState
PCIeLinkUp L0
Manageability/Wake
4
5
7
Dr
8
9
10
3
Power
Power‐On‐Reset
(internal)
2
PCIe
referenceclock
PERST#
Xosc
1
6
txog
tee tee
11 12
tpgtrn
13
tpgres
tpgcfg
tPWRGD‐CLK
tPVPGL
tppg
Auto
Read
Ext.
Conf.
Auto
Read
Ext.
Conf.
nwoD/evitcAnwod‐derewoP