Data Sheet

Ethernet Controller I210 —Interconnects
130
3.7.8.7.3.14 Polarity Correction
The PHY automatically detects and corrects for the condition where the receive signal (MDI_PLUS[0]/
MDI_MINUS[0]) is inverted. Reversed polarity is detected if eight inverted link pulses or four inverted
end-of-frame markers are received consecutively. If link pulses or data are not received for 96-130 ms,
the polarity state is reset to a non-inverted state.
Automatic polarity correction can be disabled by setting bit PHYREG 0,16 bit 1.
3.7.8.7.3.15 Dribble Bits
The PHY handles dribble bits for all of its modes. If between one and four dribble bits are received, the
nibble is passed across the interface. The data passed across is padded with 1's if necessary. If
between five and seven dribble bits are received, the second nibble is not sent onto the internal MII bus
to the MAC. This ensures that dribble bits between 1-7 do not cause the MAC to discard the frame due
to a CRC error.
3.7.8.7.3.16 PHY Address
The external PHY MDIO Address is defined in the MDICNFG.PHYADD field and is loaded at power-up
from the Flash. If the MDICNFG.Destination bit is cleared (internal PHY), MDIO access is always to the
internal PHY.