Data Sheet

Ethernet Controller I210 —Interconnects
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3. Device off mode - Internal PHY can be disabled if the DEV_OFF_N pin is asserted. Since the PHY is
shared between the LAN function and manageability, it might not be desirable to power down the
PHY in Device Disable mode. The PHY_in_LAN_Disable Flash bit determines whether the PHY (and
MAC) are powered down when the DEV_OFF_N pin is asserted. The default is to power down.
Note: If the LPLU, Disable 1000 in Non-D0a or the Disable 100 in Non-D0a Flash bits are set and the
MANC.Keep_PHY_Link_Up bit (Veto bit) is cleared, Management may operate with reduced
link speed since the function is in a Non-D0a (uninitialized) state.
3.7.8.6 Advanced Diagnostics
The I210 integrated PHY incorporates hardware support for advanced diagnostics.
The hardware support enables output of internal PHY data to host memory for post processing by the
software device driver.
The current diagnostics supported are described in the sections that follow.
3.7.8.6.1 Time Domain Reflectometry (TDR)
By sending a pulse onto the twisted pair and observing the retuned signal, the following can be
deduced:
1. Is there a short?
2. Is there an open?
3. Is there an impedance mismatch?
4. What is the length to any of these faults?
3.7.8.6.2 Channel Frequency Response
By doing analysis on the Tx and Rx data, it can be established that a channel’s frequency response
(also known as insertion loss) can determine if the channel is within specification limits. (Clause
40.7.2.1 in IEEE 802.3).
3.7.8.7 1000 Mb/s Operation
3.7.8.7.1 Introduction
Figure 3-18 shows an overview of 1000BASE-T functions, followed by discussion and review of the
internal functional blocks.