Data Sheet

Ethernet Controller I210 —Interconnects
120
3.7.8.5.1 Power Down via the PHY Register
The PHY can be powered down using the control bit found in PHYREG 0,0.11. This bit powers down a
significant portion of the port but clocks to the register section remain active. This enables the PHY
management interface to remain active during register power down. The power down bit is active high.
When the PHY exits software power-down (PHYREG 0,0.11 = 0b), it re-initializes all analog functions,
but retains its previous configuration settings.
3.7.8.5.2 Power Management State
The internal PHY is aware of the power management state. If the PHY is not in a power down state,
then PHY behavior regarding several features are different depending on the power state, refer to
Section 3.7.8.5.4.
3.7.8.5.3 Disable High Speed Power Saving Options
The I210 supports disabling 1000 Mb/s or both 1000 Mb/s and 100 Mb/s advertisement by the internal
PHY regardless of the values programmed in the PHY ANA Register (address - 4d) and the PHY GCON
Register (address - 9d).
This is for cases where the system doesn't support working in 1000 Mb/s or 100 Mb/s due to power
limitations.
This option is enabled in the following PHPM register bits:
• PHPM.Disable 1000 in non-D0a - disable 1000 Mb/s when in non-D0a states only.
• PHPM.Disable 100 in non-D0a - disable 1000 Mb/s and 100 Mb/s when in non-D0a states only.
• PHPM.Disable 1000 - disable 1000 Mb/s always.
Note: When Value of PHPM.Disable 1000 bit is changed, PHY initiates auto-negotiation without
direct driver command.
3.7.8.5.4 Low Power Link Up - Link Speed Control
Normal internal PHY speed negotiation drives to establish a link at the highest possible speed. The I210
supports an additional mode of operation, where the PHY drives to establish a link at a low speed. The
link-up process enables a link to come up at the lowest possible speed in cases where power is more
important than performance. Different behavior is defined for the D0 state and the other non-D0
states.