Data Sheet

Interconnects—Ethernet Controller I210
119
3.7.8.3 Flow Control
Flow control is a function that is described in Clause 31 of the IEEE 802.3 standard. It enables
congested nodes to pause traffic. Flow control is essentially a MAC-to-MAC function. MACs indicate their
ability to implement flow control during auto-negotiation. This ability is communicated through two bits
in the auto-negotiation registers (PHYREG 0,4.10 and PHYREG 0,4.11).
The PHY transparently supports MAC-to-MAC advertisement of flow control through its auto-negotiation
process. Prior to auto-negotiation, the MAC indicates its flow control capabilities via PHYREG 0,4.10
(Pause) and PHYREG 0,4.11 (ASM_DIR). After auto-negotiation, the link partner's flow control
capabilities are indicated in PHYREG 0,5.10 and PHYREG 0,5.11.
There are two forms of flow control that can be established via auto-negotiation: symmetric and
asymmetric. Symmetric flow control is for point-to-point links; asymmetric for hub-to-end-node
connections. Symmetric flow control enables either node to flow-control the other. Asymmetric flow-
control enables a repeater or switch to flow-control a DTE, but not vice versa.
Table 3-31 lists the intended operation for the various settings of ASM_DIR and PAUSE. This
information is provided for reference only; it is the responsibility of the MAC to implement the correct
function. The PHY merely enables the two MACs to communicate their abilities to each other.
3.7.8.4 Management Data Interface
The PHY supports the IEEE 802.3 MII Management Interface also known as the Management Data
Input/Output (MDIO) Interface. This interface enables upper-layer devices to monitor and control the
state of the PHY. The MDIO interface consists of a physical connection, a specific protocol that runs
across the connection, and an internal set of addressable registers.
The PHY supports the core 16-bit MDIO registers. Registers 0-10 and 15 are required and their
functions are specified by the IEEE 802.3 specification. Additional registers are included for expanded
functionality. Specific bits in the registers are referenced using an PHY REG X.Y notation, where X is the
register number (0-31) and Y is the bit number (0-15).
3.7.8.5 Internal PHY Low Power Operation and Power Management
The internal PHY incorporates numerous features to maintain the lowest power possible.
The PHY can be entered into a low-power state according to MAC control (Power Management controls)
or via PHY Register 0. In either power down mode, the PHY is not capable of receiving or transmitting
packets.
Table 3-31. Pause And Asymmetric Pause Settings
ASM_DIR Settings Local
(PHYREG 0,4.10) and
Remote (PHYREG 0,5.10)
Pause Setting -
Local (PHYREG
0,4.11)
Pause Setting -
Remote (PHYREG
0,5.11)
Result
Both ASM_DIR = 1b 1b 1b Symmetric - Either side can flow control the other.
1b 0b Asymmetric - Remote can flow control local only.
0b 1b Asymmetric - Local can flow control remote.
0b 0b No flow control.
Either or both ASM_DIR = 0b 1b 1b Symmetric - Either side can flow control the other.
Either or both = 0b No flow control.