Data Sheet

Interconnects—Ethernet Controller I210
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6. Set the LTRC.EEEMS_EN bit to 1b, to enable sending an updated PCIe LTR message when detecting
a link partner entry into EEE Rx LPI state.
Notes:
1. The LTRC.EEEMS_EN bit is cleared following link disconnect or auto-negotiation and should be set
to 1b by software following EEE LLDP re-negotiation.
2. The I210 waits for at least 1 second following auto-negotiation (due to reset, link disconnect, or link
speed change) and link-up indication (STATUS.LU set to 1b, refer to Section 8.2.2) before enabling
link entry into EEE Tx LPI state to comply with the IEEE802.3az specification.
3.7.7.5.1 PHY Programming for EEE Operation with Cables > 130m
When working with cables long by 130 meters and beyond, it is recommended that the following PHY
register settings be applied by host to improve EEE interoperability with third part vendors:
1. Reg 22 = 0x00FF
2. Reg 17 = 0x0048
3. Reg16 = 0X215D
4. Reg 17 = 0x0027
5. Reg16 = 0X2150
6. Reg 17 = 0xDC0C
7. Reg16 = 0X2159
8. Reg 17 = 0xA42B
9. Reg16 = 0X2151
10. Reg 17 = 0x3024
11. Reg16 = 0X215C
12. Reg 22 = 0x00FC
13. Reg 24 = 0x888E
14. Reg 25 = 0x888E
15. Reg 1 = 0x20B0
These settings can be applied before the link is up when EEE is enabled.
3.7.7.6 EEE Statistics
The I210 supports reporting the number of EEE LPI Tx and Rx events via the RLPIC and TLPIC registers.
3.7.8 Integrated Copper PHY Functionality
The register set used to control the PHY functionality (PHYREG) is described in Section 8.27.3. the
registers can be programmed using the MDIC register (refer to Section 8.2.4).
3.7.8.1 Determining Link State
The PHY and its link partner determine the type of link established through one of three methods:
•Auto-negotiation
• Parallel detection