Data Sheet

Interconnects—Ethernet Controller I210
107
— Set speed using bits 6 and 13. Register values should be:
• For 10 Mb/s 0x4100
• For 100 Mb/s 0x6100
• For 1000 Mb/s 0x4140
— Use bits 2:0 in PHYREG 2,21 to control the link speed in MDI loopback
— reset the PHY – in PHYREG 0,0 Set Copper Reset bit (bit 15)
— In PHYREG 0,0 Set loopback bit (bit 14)
3.7.6.4 SerDes, SGMII and 1000BASE-KX Loopback
In SerDes, SGMII or 1000BASE-KX loopback, the PHY block is not functional and data is looped back at
the end of the relevant functionality. This means all designs that are functional in SerDes/SGMII or
1000BASE-KX mode, are involved in the loopback.
Note: SerDes loopback is functional only if the SerDes link is up.
3.7.6.4.1 Setting the I210 to SerDes/1000BASE-BX, SGMII or 1000BASE-KX Loopback
Mode
The following procedure should be used to place the I210 in SerDes loopback mode:
• Set Link mode to either SerDes, SGMII or 1000BASE-KX by:
— 1000BASE-KX: CTRL_EXT.LINK_MODE = 01b
— SGMII: CTRL_EXT.LINK_MODE = 10b
— SerDes/1000BASE-BX: CTRL_EXT.LINK_MODE = 11b
• Configure SerDes to loopback: RCTL.LBM = 11b
• Move to Force mode by setting the following bits:
— CTRL.FD (CSR 0x0 bit 0) = 1b
— CTRL.SLU (CSR 0x0 bit 6) = 1b
— CTRL.RFCE (CSR 0x0 bit 27) = 0b
— CTRL.TFCE (CSR 0x0 bit 28) = 0b
— PCS_LCTL.FORCE_LINK (CSR 0X4208 bit 5) = 1b
— PCS_LCTL.FSD (CSR 0x4208 bit 4) = 1b
— PCS_LCTL.FDV (CSR 0x4208 bit 3) = 1b
— PCS_LCTL.FLV (CSR 0x4208 bit 0) = 1b
— PCS_LCTL.AN_ENABLE (CSR 0x4208 bit 16) = 0b
3.7.6.5 External PHY Loopback
In external PHY loopback, the SerDes block is not functional and data is sent through the MDI interface
and looped back using an external loopback plug. This means that all designs that are functional in
copper mode are involved in the loopback. If connected at 10/100 Mb/s, the loopback operates without
any special setup. For 1000 Mb/s operation, see the section that follows.