Data Sheet

Ethernet Controller I210 —Interconnects

106

Figure 3-12. I210 Loopback Modes

In addition, The I210’s copper PHY support a far end loopback mode, where incoming traffic is reflected

at the PHy level onto the transmit wires. This mode is entered by setting bit 14 in PHY register Page 2,

3.7.6.2 MAC Loopback

In MAC loopback, the PHY and SerDes blocks are not functional and data is looped back before these

blocks.

3.7.6.2.1 Setting the I210 to MAC loopback Mode

The following procedure should be used to put the I210 in MAC loopback mode:

•Set RCTL.LBM to 01b (bits 7:6)

•Set CTRL.SLU (bit 6, should be set by default)

•Set CTRL.FRCSPD and FRCDPLX (bits 11 and 12)

•Set the CTRL.FD bit and program the CTRL.SPEED field to 10b (1 GbE).

•Set EEER.EEE_FRC_AN to 1b to enable checking EEE operation in MAC loopback mode.

Filter configuration and other Tx/Rx processes are the same as in normal mode.

3.7.6.3 Internal PHY Loopback

In PHY loopback, the SerDes block is not functional and data is looped back at the end of the PHY

functionality. This means all the design, that is functional in copper mode, is involved in the loopback.

3.7.6.3.1 Setting the I210 to Internal PHY loopback Mode

The following procedure should be used to place the I210 in PHY loopback mode on the LAN port:

• Set Link mode to Internal PHY: CTRL_EXT.LINK_MODE = 00b.

• In the PHY control register (PHYREG 0,0 - Address 0 in the PHY):

— Set duplex mode (bit 8)

— Clear auto-negotiation enable bit (bit 12)

MAC

Packet Buffer

and DMA

SerDes

Interface

Internal

PHY

SerDes/

SGMII

1GbT

GMII

PCIe