Intel® Ethernet Controller I210 Datasheet Networking Division (ND) Features: • • • • • • • • Small package: 9 x 9 mm PCIe v2.1 (2.5 GT/s) x1, with Switching Voltage Regulator (iSVR) Integrated Non-Volatile Memory (iNVM) Three single port SKUs: SerDes, Copper, Copper IT Value Part (Intel® Ethernet Controller I211) Platform Power Efficiency — IEEE 802.
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Revision History—Ethernet Controller I210 Revision History Rev Date Notes June 2018 Updated Section 7.2.2.2.3 [LaunchTime (25)] 3.2 January 2018 Updated Table 2-1 (Pull-Up/Pull-Down Resistors). Added section 3.3.2.4 (iNVM Structure Version Information). Updated section 5.5.6 (Timing Guarantees). Updated section 6.8.2 (Port Identification LED Blinking; Word 0x04). Updated section 11.8.1 (Flash Parts). 3.1 June 2017 Revised Section: • 3.4.3 (iNVM Programming Flows).
Ethernet Controller I210 —Revision History Rev Date Notes • • Revised section 1.3.1 (Audio/Video Bridging Support). Revised section 6.7.1.2 (Common Firmware Parameters 1 - Offset 0x1; bit 15). Revised section 7.1.2.10 (Receive-Side Scaling (RSS). Revised section 7.8.3.1 (Capture Timestamp Mechanism). Revised section 8.21.18 (Flexible Host Filter Table Registers - FHFT (0x9000 + 4*n [n=0...255]; RW); updated note. Revised section 8.27.3.
Introduction—Ethernet Controller I210 1.0 Introduction The Intel® Ethernet Controller I210 (I210) is a single port, compact, low power component that supports GbE designs. The I210 offers a fully-integrated GbE Media Access Control (MAC), Physical Layer (PHY) port and a SGMII/SerDes port that can be connected to an external PHY. The I210 supports PCI Express* [PCIe v2.1 (2.5GT/s)]. The I210 enables 1000BASE-T implementations using an integrated PHY.
Ethernet Controller I210 —Introduction Table 1-1. Glossary (Continued) Definition DFT Meaning Design for Testability. DQ Descriptor Queue. DMTF Distributed Management Task Force standard body. DW Double word (4 bytes). EEE Energy Efficient Ethernet - IEEE802.3az standard EEPROM Electrically Erasable Programmable Memory. A non-volatile memory located on the LAN controller that is directly accessible from the host. EOP End of Packet. FC Flow Control. FCS Frame Check Sequence.
Introduction—Ethernet Controller I210 Table 1-1. Glossary (Continued) Definition Meaning PHY Physical Layer Device. PMA Physical Medium Attachment. PMD Physical Medium Dependent. SA Source Address. SDP Software Defined Pins. SerDes Serializer/deserializer. A transceiver that converts parallel data to serial data and vice-versa. SFD Start Frame Delimiter. SGMII Serialized Gigabit Media Independent Interface. SMBus System Management Bus.
Ethernet Controller I210 —Introduction 1.2.1.2 Host Interface Documents 1. PCI-Express 2.1 Base specification 2. PCI Specification, version 3.0 3. PCI Bus Power Management Interface Specification, Rev. 1.2, March 2004 4. Advanced Configuration and Power Interface Specification, Rev 2.0b, October 2002 1.2.1.3 Networking Protocol Documents 1. IPv4 specification (RFC 791) 2. IPv6 specification (RFC 2460) 3. TCP/UDP specification (RFC 793/768) 4. SCTP specification (RFC 2960) 5.
Introduction—Ethernet Controller I210 1.3.1 Audio/Video Bridging Support The I210 supports IEEE 802.1 Audio Video Bridging (AVB) specifications. The draft AVB standards are designed to work over widely-used IEEE 802 layer 2 networks. These new standards provide networking features for tightly controlled media stream synchronization, buffering and reservation. The IEEE 802.1AVB task group is working on an interoperability standards for systems based on the AVB document set.
Ethernet Controller I210 —Introduction Note: 1.4.4 When operated in Flash-less mode with an external PHY (such as the I210 SGMII SKU), no link up is made possible after power up before the driver configures the external PHY. It means that in such case, WoL is not supported when the system passes through the following states: G3 --> S5 --> WoL.
Introduction—Ethernet Controller I210 1.4.8 Software-Definable Pins (SDP) Interface (General-Purpose I/O) The I210 has four software-defined pins (SDP pins) that can be used for IEEE1588 auxiliary device connections, enable/disable of the device, and for other miscellaneous hardware or software-control purposes. These pins can be individually configurable to act as either standard inputs, General-Purpose Interrupt (GPI) inputs or output pins (refer to Section 6.2.21, Section 8.2.1 and Section 8.2.
Ethernet Controller I210 —Introduction Table 1-3. Network Features Feature I210 I211 I350 82574 Y Y Y Y 1 port 1 port 4 ports 1 port Half duplex at 10/100 Mb/s operation and full duplex operation at all supported speeds 10/100/1000 copper PHY integrated on-chip Jumbo frames supported Y Y Y Y 9.5 KB 9.5 KB 9.
Introduction—Ethernet Controller I210 Table 1-4.
Ethernet Controller I210 —Introduction Table 1-6.
Introduction—Ethernet Controller I210 Table 1-7. Virtualization Related Features (Continued) I210 I211 I350 82574 External switch VEPA support Feature N N Y N External switch NIV (VNTAG) support N N N N VLAN, unicast multicast VLAN, unicast multicast unicast multicast VLAN, unicast multicast Promiscuous modes Table 1-8.
Ethernet Controller I210 —Introduction Table 1-9. Power Management Features Feature I210 I211 I350 82574 Y1 Y1 Y Y Y LAN disable functionality (equivalent to Static device off functionality in the I210/I211) PCIe function disable Y Y Y Dynamic device off Y2 Y2 Y Y EEE Y Y Y N DMA coalescing Y N Y N N N N OBFF/PE_WAKE_N Y 3 1. Feature not functional if enabled together with dynamic device off. 2.
Introduction—Ethernet Controller I210 1.7.1.2 OBFF The I210 support Optimized Buffer Flush Fill (OBFF) for synchronizing platform I/Os and optimizing CPU sleep states. The support is via the PE_WAKE_N pin only. 1.7.2 Audio and Video Bridging Support See Section 1.3.1 for details on IEEE 802.1Qav support. 1.7.2.1 Tx Timestamp The I210 supports three types of transmit timestamps: 1. Reporting back of the timestamp in the transmit descriptor. 2. Inserting the timestamp in the packet sent. 3.
Ethernet Controller I210 —Introduction 1.7.5 Manageability 1.7.5.1 DMTF MCTP Protocol Over PCIe The I210 enables reporting and controlling all information exposed in a LOM device via NC-SI using the MCTP protocol over PCIe in addition to SMBus. The MCTP interface over PCIe is used by the MC to control the NIC and for pass through traffic. For more information, refer to Section 10.7. 1.7.5.2 Flash Structures Management related Flash structures were updated. For further information see Chapter 6.0.
Introduction—Ethernet Controller I210 Table 1-11. Transmit Data Flow Step Description 1 The host creates a descriptor ring and configures one of the I210's transmit queues with the address location, length, head and tail pointers of the ring (one of 4 available Tx queues). 2 The host is requested by the TCP/IP stack to transmit a packet, it gets the packet data within one or more data buffers.
Ethernet Controller I210 —Introduction Table 1-12. Receive Data Flow (Continued) Step Description 10 After the entire packet is placed into the Rx FIFO, the receive DMA posts the packet data to the location indicated by the descriptor through the PCIe interface. If the packet size is greater than the buffer size, more descriptors are fetched and their buffers are used for the received packet.
Pin Interface—Ethernet Controller I210 2.0 Pin Interface 2.1 Pin Assignments The I210 supports a 64-pin, 9 x 9 QFN package with an Exposed Pad* (e-Pad*). Note that the e-Pad is ground. LED2 SMB_CLK SMB_ALRT_N SMB_DAT CBOT VDD0p9_OUT VDD1p5_OUT CTOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 I210 64-Pin QFN 9 mm x 9mm 0.
Ethernet Controller I210 —Pin Interface 2.2 Pull-Up/Pull-Down Resistors Table 2-1 lists internal and external pull-up/pull-down resistors and their functionality in different device states. • As stated in the name and function table columns, the internal Pull-Up/Pull-Down (PU/PD) resistor values are 30 K ± 50%. • Only relevant (digital) pins are listed; analog or bias and power pins have specific considerations listed in Chapter 11.0. Note: Refer to Section 12.
Pin Interface—Ethernet Controller I210 Table 2-1. Pull-Up/Pull-Down Resistors (Continued) Power Up1 Signal Name PU Disable2 Active Comments PU Comments Until Flash autoload done PU Y External Comments Might keep state by Flash control N SDP3 Y Y DEV_OFF_N Y N N PU optional if NC-SI is not used.
Ethernet Controller I210 —Pin Interface 2.3.1 PCIe Table 2-2. PCIe Symbol Reserved Lead # PECLKp PECLKn 26 25 PE_Tp PE_Tn 21 20 PE_Rp PE_Rn 24 23 Type Op Mode Name and Function Input PCIe Differential Reference Clock In This pin receives a 100 MHz differential clock input. This clock is used as the reference clock for the PCIe Tx/Rx circuitry and by the PCIe core PLL to generate a 125 MHz clock and 250 MHz clock for the PCIe core logic.
Pin Interface—Ethernet Controller I210 2.3.3 System Management Bus (SMBus) Interface Table 2-4. SMBus Interface Symbol Reserved Lead # Type Op Mode Name and Function SMB_DATA 36 T/s, o/d Bi-dir SMBus Data. Stable during the high period of the clock (unless it is a start or stop condition). SMB_CLK 34 T/s, o/d Bi-dir SMBus Clock. One clock pulse is generated for each data bit transferred. SMB_ALRT_N 35 T/s, o/d Output SMBus Alert.
Ethernet Controller I210 —Pin Interface 2.3.5 LEDs Table 2-6 lists the functionality of each LED output pin. The default activity of each LED can be modified in the Flash. The LED functionality is reflected and can be further modified in the configuration registers (LEDCTL). Table 2-6. Symbol LEDs Reserved Lead # Type Op Mode Name and Function LED0 31 Out Output Programmable LED number 0. LED1 30 Out Output Programmable LED number 1. LED2 33 Out Output Programmable LED number 2. 2.3.
Pin Interface—Ethernet Controller I210 Table 2-7. PHY Pins Symbol MDI_PLUS[1]/ SFP_I2C_CLK MDI_MINUS[1]/ SRDS_SIG_DET Lead # 55 54 Type A A Op Mode Name and Function Bi-dir In BASE-T: Media Dependent Interface[1]: 1000BASE-T: In MDI configuration, MDI[1]+ corresponds to BI_DB+ and in MDI-X configuration MDI[1]+ corresponds to BI_DA+. 100BASE-TX: In MDI configuration, MDI[1]+ is used for the receive pair and in MDI-X configuration MDI[1]+ is used for the transmit pair.
Ethernet Controller I210 —Pin Interface 2.3.7 Miscellaneous Pins Table 2-8. Miscellaneous Pins Symbol Reserved Lead # Type Op Mode Name and Function DEV_OFF_N 28 In Input This is a 3.3V input signal. Asserting DEV_OFF_N puts the I210 in device disable mode. Note that this pin is asynchronous. Functionality of this input can be changed by Flash bits settings - see Table 2-11 for more details. SDP0 63 T/s Input/ Output Software defined pin 0.
Pin Interface—Ethernet Controller I210 2.3.8.2 Power Supply Table 2-10. Power Supply Symbol Lead # Type / Voltage Name and Function VDD0p9 11, 32, 42, 59 0.9V 0.9V digital power supply. VDD3p3 10, 27, 41, 51, 64 3.3V 3.3V power supply (for I/O). Pin 51: In BASE-T, 3.3V analog power supply to GPHY; in SerDes, 1.5V analog power supply to SGMII SerDes. VDD1p5 47, 56 1.5V Pin 47: 1.5V power supply to the crystal oscillator and bandgap. Pin 56: In BASE-T, 1.
Ethernet Controller I210 —Pin Interface 2.4 Strapping Options Table 2-11. Strapping Options Pad NVM PU 0x1E.15 0x29.10 0x29.13 0x29.15 SDP1 [PCIe_DIS] Device Off Enable nvm_aux_pwr_en nvm_alt_aux_pwr_en en_pin_pcie_func_dis X X X 1 X X X Device off mode when the pin is pulled low. AUX_PWR (option 1) N/A 1 X X X X 0 1 X X AUX power mode when the pin is pulled high. AUX_PWR (option 2) N/A X 1 X X X 0 0 1 X AUX power mode when the pin is pulled high.
Pin Interface—Ethernet Controller I210 2.5 Package The I210 supports a 64-pin, 9 x 9 QFN package with e-Pad. Figure 2-2 shows the package schematics. Die Pad Size Option Symbol Figure 2-2.
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Interconnects—Ethernet Controller I210 3.0 Interconnects 3.1 PCIe 3.1.1 PCIe Overview PCIe is a third generation I/O architecture that enables cost competitive next generation I/O solutions providing industry leading price/performance and features. It is an industry-driven specification. PCIe defines a basic set of requirements that encases the majority of the targeted application classes.
Ethernet Controller I210 —Interconnects PCIe's physical layer consists of a differential transmit pair and a differential receive pair. Full-duplex data on these two point-to-point connections is self-c such that no dedicated clock signals are required. The bandwidth of this interface increases linearly with frequency. The packet is the fundamental unit of information exchange and the protocol includes a message space to replace the various side-band signals found on many buses today.
Interconnects—Ethernet Controller I210 — Active state power management • Support for PCIe v2.1 (2.5GT/s) — Support for completion time out — Support for additional registers in the PCIe capability structure. 3.1.1.2 Physical Interface Properties • Point to point interconnect — Full-duplex; no arbitration • Signaling technology: — Low Voltage Differential (LVD) — Embedded clock signaling using 8b/10b encoding scheme • Serial frequency of operation: 2.5 Gb/s. • Interface width of x1.
Ethernet Controller I210 —Interconnects The PCIe function interfaces with the PCIe unit through one or more clients. A client ID identifies the client and is included in the Tag field of the PCIe packet header. Completions always carry the tag value included in the request to enable routing of the completion to the appropriate client. Tag IDs are allocated differently for read and write. Messages are sent with a tag of 0x0. 3.1.3.1.
Interconnects—Ethernet Controller I210 Table 3-2. IDs in Write Transactions (DCA Disabled Mode) Tag ID Description 0x0 - 0x1 Reserved 0x2 Tx descriptors write-back / Tx head write-back 0x3 Reserved 0x4 Rx descriptors write-back 0x5 Reserved 0x6 Write data 0x7 - 0x1D Reserved 0x1E MSI and MSI-X 0x1F Reserved 3.1.3.1.2.
Ethernet Controller I210 —Interconnects • Disabling or enabling completion timeout. • Disabling or enabling re-send of a request on completion timeout. • A programmable range of re-sends on completion timeout, if re-send enabled. • A programmable range of timeout values. • Programming the behavior of completion timeout is listed in Table 3-3. Table 3-3.
Interconnects—Ethernet Controller I210 3.1.4.1 Transaction Types Accepted by the I210 Table 3-4.
Ethernet Controller I210 —Interconnects 3.1.4.2 Transaction Types Initiated by the I210 Table 3-5.
Interconnects—Ethernet Controller I210 The PCIe specification does not ensure that completions for separate requests return in-order. Read completions for concurrent requests are not required to return in the order issued. The I210 handles completions that arrive in any order. Once all completions arrive for a given request, the I210 might issue the next pending read data request. • The I210 incorporates a re-order buffer to support re-ordering of completions for all requests.
Ethernet Controller I210 —Interconnects 3.1.4.3.2 Message Handling by I210 (as a Transmitter) The transaction layer is also responsible for transmitting specific messages to report internal/external events (such as interrupts and PMEs). Table 3-7.
Interconnects—Ethernet Controller I210 +0 7 6 5 FMT 011 4 +1 3 2 Type 10r2r1r0 1 0 7 6 R TC 000 5 4 +2 3 2 1 0 7 6 R A tt r R T H T D E P 5 4 Attr [1:0] 3 AT 00 +3 2 1 0 R PCI Target ID (For Route by ID messages, otherwise = Reserved) Pad Len 6 5 4 3 2 1 0 Length 00_000x_xxxx PCI Tag Field PCI Requester ID 7 MCTP VDM code - 0000b Message Code Vendor Defined = 0111_1111b Vendor ID = 0x1AB4 (DMTF) Figure 3-2. MCTP over PCIe VDM Header Format 3.1.4.
Ethernet Controller I210 —Interconnects 3.1.4.5 Transaction Definition and Attributes 3.1.4.5.1 Max Payload Size The I210 policy to determine Max Payload Size (MPS) is as follows: • Master requests initiated by the I210 (including completions) limits MPS to the value defined for the function issuing the request. • Target write accesses to the I210 are accepted only with a size of one Dword or two Dwords. Write accesses in the range of (three Dwords, MPS, etc.) are flagged as UR.
Interconnects—Ethernet Controller I210 Table 3-8 lists software configuration for the No-Snoop and Relaxed Ordering bits for LAN traffic when I/OAT 2 is enabled. Table 3-8. LAN Traffic Attributes Transaction No-Snoop Relaxed Ordering Rx Descriptor Read N Y Rx Descriptor Write-Back N N Relaxed ordering must never be used for this traffic. Rx Data Write Y Y Refer to Note 1 and Section 3.1.4.5.4.
Ethernet Controller I210 —Interconnects 3.1.4.6 Flow Control 3.1.4.6.1 I210 Flow Control Rules The I210 implements only the default Virtual Channel (VC0). A single set of credits is maintained for VC0. Table 3-9.
Interconnects—Ethernet Controller I210 After timer expiration, the mechanism instructs the PHY to re-establish the link (via the LTSSM recovery state). 3.1.4.7 Error Forwarding If a TLP is received with an error-forwarding trailer (poisoned TLP received), the transaction can either be resent or dropped and not delivered to its destination, depending on the GCR.Completion Timeout resend enable bit and the GCR.Number of resends field.
Ethernet Controller I210 —Interconnects The following DLLPs are supported by the I210 as a transmitter: Table 3-11.
Interconnects—Ethernet Controller I210 3.1.6.3 Polarity Inversion If polarity inversion is detected, the receiver must invert the received data. During the training sequence, the receiver looks at Symbols 6-15 of TS1 and TS2 as the indicator of lane polarity inversion (D+ and D- are swapped). If lane polarity inversion occurs, the TS1 Symbols 615 received are D21.5 as opposed to the expected D10.2. Similarly, if lane polarity inversion occurs, Symbols 6-15 of the TS2 ordered set are D26.
Ethernet Controller I210 —Interconnects Table 3-12. Response and Reporting of PCIe Error Events Error Name Error Events Default Severity Action PHY errors Receiver error 8b/10b decode errors Packet framing error Correctable. Send ERR_CORR TLP to initiate NAK and drop data. DLLP to drop. Data link errors Bad TLP • • • Bad CRC Not legal EDB Wrong sequence number Correctable. Send ERR_CORR TLP to initiate NAK and drop data. Bad DLLP • Bad CRC Correctable. Send ERR_CORR DLLP to drop.
Interconnects—Ethernet Controller I210 Table 3-12. Response and Reporting of PCIe Error Events (Continued) Error Name Error Events • • Malformed TLP (MP) • • • Data payload exceed Max_Payload_Size Received TLP data size does not match length field TD field value does not correspond with the observed size Power management messages that doesn’t use TC0. Usage of unsupported VC. Completion with unsuccessful completion status Byte count integrity in completion process. 3.1.7.
Ethernet Controller I210 —Interconnects 3.1.7.5 Partial Read and Write Requests 3.1.7.5.1 Partial Memory Accesses The I210 has limited support of read/write requests with only part of the byte enable bits set: • Partial writes with at least one byte enabled should not be used. If used, the results are unexpected, either the byte enable request is honored or the entire Dword is written. • Zero-length writes has no internal impact (nothing written, no effect such as clear-by-write).
Interconnects—Ethernet Controller I210 2. Changes in the response to some uncorrectable non-fatal errors, detected in non-posted requests to the I210. These are called advisory non-fatal error cases. For each of the errors that follow, the following behavior is defined: a.
Ethernet Controller I210 —Interconnects 3.2 Management Interfaces The I210 contains three possible interfaces to an external MC. • SMBus • NC-SI • MCTP (over PCIe or SMBus) 3.2.1 SMBus SMBus is an optional interface for pass-through and/or configuration traffic between an external MC and the I210. The SMBus channel behavior and the commands used to configure or read status from the I210 are described in Section 10.5.
Interconnects—Ethernet Controller I210 3.2.2.2 NC-SI Transactions The NC-SI link supports both pass-through traffic between the MC and the I210 LAN functions, as well as configuration traffic between the MC and the I210 internal units as defined in the NC-SI protocol. Refer to Section 10.6.2 for information. 3.2.3 MCTP (over PCIe or SMBus) The I210 supports MCTP protocol for management. MCTP runs over PCIe or SMBus. The I210 implements NC-SI over MCTP protocol for command and pass through traffic. 3.
Ethernet Controller I210 —Interconnects The following OpCodes must be supported by the I210 as they are common to all the supported Flash devices: Name Opcode Description WREN 0x6 Write Enable RDID 0x9f Read JEDEC Manufacture ID WRSR 0x1 Write Status READ 0x3 Flash Read RDSR 0x5 Read Flash Status Sector Erase 0x20 4 KB Sector Erase Flash Erase 0xc7 Flash Erase Page Program 0x2 Write to the Flash Fast Read Read data bytes at higher speed 0x0b The other OpCodes to be supported ar
Interconnects—Ethernet Controller I210 As a physical recovery method required for manufacturing, the non-secure mode can also be entered by setting a strapping option. Only host access to Flash and shadow RAM is guaranteed when in this mode.
Ethernet Controller I210 —Interconnects Flash I210 0xFFFFFF 0xFFFFFF 0x000000 1:1 Flash-Mode Access 0x002000 0x001FFF 4KB Sector 1 0x001000 0x000FFF 4KB Sector 0 0x000000 0x000FFF Shadow RAM Physical Byte address Figure 3.3. 0x000FFF 0x000000 0x000000 Internal RAM address EEPROMMode Access Logical address Flash Shadow RAM Following a write access by software or firmware to the shadow RAM, the data should finally be updated in the Flash as well.
Interconnects—Ethernet Controller I210 Besides these configurable protected areas, some fixed Flash words in the Flash header are also writeprotected from host (RO for host, RW for manageability). It concerns mainly pointers to Flash modules and other Flash words that are critical for the host to device connectivity over PCIe. Refer to the right-most column in Table 6-1 for the list of protected words. Any host attempt to write a protected area or word is silently discarded.
Ethernet Controller I210 —Interconnects 3.3.3.1 Memory Mapped Host Interface The Flash device can be mapped into memory and/or I/O address space of the PF through the use of Base Address Registers (BARs). Clearing the FLBAR_Size and CSR_Size fields in PCIe Control 2 Flash word (Word 0x28) to 0b, disables Flash mapping to PCI space via the Flash Base Address register.
Interconnects—Ethernet Controller I210 The I210 controls accesses to the Flash when it decodes a valid access. Attempts to out-of-range write access the PCIe Expansion/Option ROM module (beyond the provisioned 512 KB) is silently ignored, while read access might return any value. The same is done for out-of-range accesses to the host memory BAR. Notes: The I210 supports four byte writes to the Flash. Byte Enable (BE) pins can be set in a consecutive way (starting from 0) for writing less than four bytes.
Ethernet Controller I210 —Interconnects FLASH IF BAR_SIZ E = 0.5MB: 0.5MB – 8KB – 1 IF BAR_SIZ E = 1MB: 1MB – 8KB – 1 BAR_SIZE – 1 Free Pro vision ing Area Seg ment Secu red Area for FW image 1 Expansion-ROM BAR Expan sio n/Option ROM Mo dule Memory BAR BAR Ad dress0x0 0x001000 0x000F FF 4 KB 0x 000800 0x0007FF Sh ado wRAM Banks 4 KB 0x 000000 BAR Ad dress0x20000 Ph ysical Flash Word Address 128KB If CSR_SIZE = 0b BAR Ad dress0x0 Figure 3-4.
Interconnects—Ethernet Controller I210 FLASH FLASH_SIZE – 1 Free Pro vision ing Area Seg ment Secu red Area for FW image 1 1MB – 8KB – 1 Expansion-ROM BAR Expan sio n/Option ROM Mo dule 0x001000 0x000F FF 0x 000000 Memory BAR BAR_SIZE BAR Add ress0x0 4 KB 0x 000800 0x0007FF FLASH_SIZE – 1 Shadow RAM Ban ks 4 KB FLASH_SIZE Ph ysical Flash Word Address BAR Address 0x20000 128KB If CSR_SIZ E = 0b BAR Address 0x0 Figure 3-5. Flash Part Size is Smaller Than BAR Size 3.3.3.
Ethernet Controller I210 —Interconnects Two software entities cannot use the semaphore mechanism: BIOS and VPD software. • Since VPD software accesses only the VPD module, which is located in the first valid sector of the Flash, VPD accesses are always performed against the shadow RAM first. In this case, firmware must take/release ownership over the Flash before dumping the VPD changes into the Flash, as if it was the originator of the Flash access. Shadow RAM dump sequence is described in Section 3.3.2.
Interconnects—Ethernet Controller I210 Cache reads can be delayed by the maximum time duration (300 ms) of a previous erase command, which was issued by firmware to hardware. Before issuing any sector erase command to hardware, firmware must complete all its pending tasks and must load from Flash the code pieces required to manage while the Flash is busy for erasing: a. For instance, NC-SI commands received are completed with the Package Not Ready status.
Ethernet Controller I210 —Interconnects Event Response PCIe to SMBus switching in MCTP mode Ignored SMBus to PCIe switching in MCTP mode Ignored NC-SI packet received Command completed with Package Not Ready error code. Any event that requires issuing an AEN Ignored All relevant events are processed right after Flash access is recovered. Command received in the host interface Ignored Commands are processed right after Flash access is recovered.
Interconnects—Ethernet Controller I210 1. Write a 1b to the Flash Request bit (FLA.FL_REQ). 2. Read the Flash Grant bit (FLA.FL_GNT) until it becomes 1b. It remains 0b as long as there are other accesses to the Flash. 3. Write or read the Flash using the direct access to the 4-wire interface as defined in the FLA register. The exact protocol used depends on the Flash placed on the board and can be found in the appropriate datasheet. 4. Write a 0b to the Flash Request bit (FLA.FL_REQ). 5.
Ethernet Controller I210 —Interconnects As a response, hardware executes the following steps: 1. Eventually clears the CMDV bit if the command cannot be currently executed, and goes to step 3. 2. The I210 writes the data to the shadow RAM. 3. The I210 sets the DONE bit in the EEWR register. Notes: The VPD area of the Flash can be accessed only via the PCIe VPD capability structure. EEPROM-mode writes are performed into the internal shadow RAM.
Interconnects—Ethernet Controller I210 10. FLSWCTL.GLDONE bit is set by hardware when the last byte programmed has been written. But software can stop the transaction in the middle as long as it got the DONE bit read as 1b. In any case, the FLBUSY bit must be read as 0b before releasing the Flash semaphore. 3.3.5.6 Software Flash Read Flow via the Flash-Mode Interface The I210 provides an engine for reading the Flash in a burst mode: 1. Poll the FLSWCTL.DONE bit until it is set.
Ethernet Controller I210 —Interconnects required the software or manageability should access the Flash one word at a time releasing the interface after each word. Software and firmware should avoid holding the Flash bit-bang interface for more than 500 ms. The deadlock timeout mechanism is enabled by the Deadlock Timeout Enable bit in the Control Word 1 in the Flash. 3.3.8 VPD Support The Flash can contain an area for VPD.
Interconnects—Ethernet Controller I210 • If the I210 does not detect a value of 0x82 in the first byte of the VPD area or if no End tag is detected, or if the structure does not follow the description of Table 3.17, it assumes the area is not programmed: — Any read/write access through the VPD registers set are ignored. — The VPD pointer itself remains RO. • The VPD RO area and RW area are both optional and can appear in any order. A single area is supported per tag type. Refer to Appendix I in the PCI 3.
Ethernet Controller I210 —Interconnects Update of the PCIe Expansion/Option ROM does not need to be protected by the double image policy as it is not as critical to the I210 operation as the firmware image module.
Interconnects—Ethernet Controller I210 4Mbit FLASH 16 K B 244 KB Free Provisioning Area mDNS Records RO Update Section Flash T able 1 244 KB Firmware Image 16 KB mDNS offset = 0x803D Secured Area C SS Header 4 KB 4 KB L egacy EEPROM (bank 1) L egacy EEPROM (bank 0) Update Sh ado wRAM EEPROM Imag e 4 KB Use Figure 3-7. Organization of the NVM That Supports 0.5 MB Flash Parts 3.3.9.
Ethernet Controller I210 —Interconnects 6. Release the Flash semaphore. a. Software must avoid taking the Flash semaphore again until the firmware resets and reloads from the new image. Any new attempt to write the Flash until then is not performed by the device. 7. If the NVM_SEC_EN bit is read as 0b (bit 13 in Flash word 0x12) or if the security-disable strapping pin is set, then firmware enters the device in the non-secured mode. 8.
Interconnects—Ethernet Controller I210 3.3.9.4 Flow for Updating One of the RW Legacy EEPROM Modules When updating one or several fields from a legacy EEPROM module there is a risk that a hardware autoload event occurs in the middle of the operation (due to a sudden PCIe reset for instance), leading to the auto-load of an invalid or inconsistent content from the internal shadow RAM into the device registers or memory.
Ethernet Controller I210 —Interconnects Integrity validation of Flash updates is provided by means of a digital signature. The digital signature is a SHA256 Hash computed over the protected content (long by 256-bits), which is then encrypted by a 2048-bits RSA encryption using an Intel private key. This digital signature is stored in what is called the manifest in the Flash module image.
Interconnects—Ethernet Controller I210 Note: The Protected Module Contents shown in Figure 3-8 starts with the I210 blank Flash Device ID word of the Flash header described in Section 6.9.1, and ends with the last word of the Firmware Secured Module - regardless to the size of the firmware code and to the presence and size of a Flash Devices Table and RO Updates sections at the last two sector of the Firmware Secured Module area. 3.3.10.
Ethernet Controller I210 —Interconnects Table 3-18.
Interconnects—Ethernet Controller I210 — Serial ID (for PCIe) is a derivative of MAC address. • iNVM image revision - word 0x05 • Subsystem ID and Subsystem Vendor ID - words 0x0B, 0x0C — Needed only for NIC and for other vendors than Intel. • Device ID - word 0x0D — Device ID: Use a separate device ID for the I211 running with a programmed iNVM (0x1539). • Board Configuration (LEDs, SDPs, etc.) - words 0x1C, 0x1F, 0x20, 0x24 • LAN power consumption - word 0x22 • PHY/PCIe analog parameters.
Ethernet Controller I210 —Interconnects Table 3-19. iNVM Structure Types Type Description 000b Un-initialized iNVM Dword, stop iNVM parsing. 001b Word auto-load 010b CSR auto-load 011b PHY register auto-load 100b Reserved - do not use this value 111b Invalidated iNVM structure, skip the Dword (16-bits) Other Reserved for future use, skip the Dword (16-bits) Table 3-20 lists the iNVM value load condition as a function of the reset types.
Interconnects—Ethernet Controller I210 Table 3-21. iNVM Values (Continued) Word Address 0x1B Word Data (16 bits) PCIe Control 1 (Word 0x1B) - Section 6.2.17 0x1C LED1 Configuration Defaults (Word 0x1C) - Section 6.2.18 0x1E Device Rev ID (Word 0x1E) - Section 6.2.19 0x1F LED0,2 Configuration Defaults (Word 0x1F) - Section 6.2.20 0x20 Software Defined Pins Control (Word 0x20) - Section 6.2.21 0x21 Functions Control (Word 0x21) - Section 6.2.22 0x22 LAN Power Consumption (Word 0x22) - Section 6.
Ethernet Controller I210 —Interconnects Once the structure is loaded to the PHY, the EEMNGCTL.CFG_DONE bit is set. 3.4.2.4 iNVM Structure (Version Information) • Bit 2:0 = Invalidated • bit 4:3 = Reserved 0x1 • bit 8:5 = Reserved 0xF • Bit 31:16 = Version number (number of 1' s show the version number 0x1 = 1, 0x3 =2, 0x7 =3, etc.) 3.4.3 iNVM Programming Flows iNVM can be programmed at several occasions and via different means: 1. At the chip manufacturing site (by Intel), via a special pin.
Interconnects—Ethernet Controller I210 8. Read the iNVM line programmed via iNVM_DATA[2n] and iNVM_DATA[2n+1] registers read. a. If not all the bits were properly written, repeat steps 4 to 8 until all bits are properly written. 9. Optionally, lock the line programmed by setting iNVM_LOCK[n].LOCK register bit to 1b. a. Wait 10 s for the lock to take effect. b. Read the iNVM_LOCK[n].LOCK register bit to check it is read as 1b. c. If it is not read as 1b, repeat step 9 until it reads as 1b. 10.
Ethernet Controller I210 —Interconnects Note: 3.4.6 Software uses the autoload bus write mechanism because writing into registers is not always possible to set internal hardware structures. I210 Init Flow Once the init flow detects no Flash device is present, a POR or a firmware reset event, the ROM-based firmware code jumps to this flow from step 2 of the flow described in Section 3.3.11.2. 1.
Interconnects—Ethernet Controller I210 However, if the system powers up in S3 state or if a firmware reset event occurs while the system was in S3, no proxy offload is performed until the system resumes S0 and the proxy code is re-loaded into the device. After PHY reset events, ROM-firmware (as well as RAM-firmware) is responsible to parse the PHY register auto-load structures of the iNVM (refer to Section 3.4.2.3) and to perform the required MDIO accesses accordingly. 3.5 Configurable I/O Pins 3.5.
Ethernet Controller I210 —Interconnects Once the host driver is up and it determines that hardware is functional, it might reset the watchdog timer to indicate that the I210 is functional. The software device driver should then re-arm the timer periodically. If the timer is not re-armed after pre-programmed timeout, an interrupt is sent to firmware and a pre-programmed SDP0 pin is asserted. Additionally the ICR.
Interconnects—Ethernet Controller I210 3.6 Voltage Regulator To reduce Bill of Material (BOM) cost, the I210 supports generating the 1.5V and 0.9V power supplies from the 3.3V supply using an on-chip Switching Capacitor Voltage Regulator (SVR) control circuit, which requires only an external capacitor component. Refer to Section 11.6.6 for more details. 3.7 Network Interfaces 3.7.1 Overview The I210 MAC provides a complete CSMA/CD function supporting IEEE 802.3 (10 Mb/s), 802.3u (100 Mb/s), 802.
Ethernet Controller I210 —Interconnects The internal copper PHY supports 10/100/1000BASE-T signaling and is capable of performing intelligent power-management based on both the system power-state and LAN energy-detection (detection of unplugged cables). Power management includes the ability to shut-down to an extremely low (powered-down) state when not needed, as well as the ability to auto-negotiate to lower-speed 10/100 Mb/s operation when the system is in low power-states. 3.7.2 MAC Functionality 3.
Interconnects—Ethernet Controller I210 The external port PHY address is written in the MDICNFG.PHYADD register field, which is loaded from the Initialization Control 4 Flash word following reset. Note: When the dedicated SFPx_I2C pins are not used for I2C, an alternative I2C interface bus can be run over SDP 0 and SDP2 pins, using the I2CCMD register set (refer to Section 3.5.2). 3.7.2.2.1 Detecting an External I2C or MDIO Connection When the CTRL_EXT.
Ethernet Controller I210 —Interconnects — Opcode = 01b (write). — REGADD = Register address of the specific register to be accessed (0 through 31). — Data = Specific data for desired control of the PHY. 3. The MAC applies the following sequence on the MDIO signal to the PHY: <01><01><10> 4. The I210 asserts an interrupt indicating MDIO Done if the Interrupt Enable bit was set. 5.
Interconnects—Ethernet Controller I210 In the case of a collision, the PHY/SGMII detects the collision and asserts the COL signal to the MAC. Frame transmission stops within four link clock times and then the I210 sends a JAM sequence onto the link. After the end of a collided transmission, the I210 backs off and attempts to re-transmit per the standard CSMA/CD method.
Ethernet Controller I210 —Interconnects The packet encapsulation is based on the Fiber Channel (FC0/FC1) physical layer and uses the same coding scheme to maintain transition density and DC balance. The physical layer device is the SerDes and is used for 1000BASE-SX, -L-, or -CX configurations.
Interconnects—Ethernet Controller I210 3.7.3.3.1 8B10B Encoding/Decoding The GbE PCS circuitry uses the same transmission-coding scheme used in the fiber channel physical layer specification. The 8B10B-coding scheme was chosen by the standards committee in order to provide a balanced, continuous stream with sufficient transition density to allow for clock recovery at the receiving station.
Ethernet Controller I210 —Interconnects 3.7.4 Auto-Negotiation and Link Setup Features The method for configuring the link between two link partners is highly dependent on the mode of operation as well as the functionality provided by the specific physical layer device (PHY or SerDes). In SerDes/1000BASE-BX mode, the I210 provides the complete PCS and Auto-negotiation functionality as defined in IEEE802.3 clause 36 and clause 37. In internal PHY mode, the PCS and IEEE802.
Interconnects—Ethernet Controller I210 Note: In internal PHY, SGMII, 1000BASE-BX and 1000BASE-KX connections, energy detect source is always internal and value of CONNSW.ENRGSRC bit should be 0b. The CTRL.ILOS bit also inverts the internal link-up input that provides link status indication and thus should be set to 0b for proper operation. 3.7.4.1.2 MAC Link Speed SerDes/1000BASE-BX operation is only defined for 1000 Mb/s operation. Other link speeds are not supported.
Ethernet Controller I210 —Interconnects Software must configure the PCS_ANADV fields to the desired advertised base page. The bits in the Device Control register are not mapped to the txConfigWord field in hardware until after autonegotiation completes. Table 3-24 lists the mapping of the PCS_ANADV fields to the Config_reg Base Page encoding per clause 37 of the standard. Table 3-24. 802.
Interconnects—Ethernet Controller I210 3.7.4.2.3 Forcing Link-up in 1000BASE-KX Mode In 1000BASE-KX mode (EXT_CTRL.LINK_MODE = 01b) the I210 should always operates in force link mode (CTRL.SLU bit is set to 1b). The MAC PCS logic is placed in a link-up state once energy indication is received, implying that a valid signal is being received by the 1000BASE-KX circuitry. When in the link-up state PCS logic can lock on incoming characters.
Ethernet Controller I210 —Interconnects 3.7.4.3.2 Forcing Link in SGMII Mode In SGMII, forcing of the link cannot be done at the PCS level, only in the external PHY. The forced speed and duplex settings are reflected by the SGMII auto-negotiation process; the MAC settings are automatically done according to this functionality. 3.7.4.3.3 MAC Speed Resolution The MAC speed and duplex settings are always set according to the SGMII auto-negotiation process. 3.7.4.
Interconnects—Ethernet Controller I210 • Software asks the MAC to attempt to auto-detect the PHY speed from the PHY-to-MAC RX_CLK, then programs the MAC speed accordingly • MAC automatically detects and sets the link speed of the MAC based on PHY indications by using the PHY's internal PHY-to-MAC speed indication (SPD_IND) Aspects of these methods are discussed in the sections that follow. 3.7.4.4.2.
Ethernet Controller I210 —Interconnects 3.7.4.4.4 Using PHY Registers The software device driver might be required under some circumstances to read from, or write to, the MII management registers in the PHY. These accesses are performed via the MDIC register (refer to Section 8.2.4).
Interconnects—Ethernet Controller I210 The implementation of asymmetric flow control allows for one link partner to send flow control packets while being allowed to ignore their reception. For example, not required to respond to PAUSE frames. The following registers are defined for the implementation of flow control: • CTRL.RFCE field is used to enable reception of legacy flow control packets and reaction to them • CTRL.
Ethernet Controller I210 —Interconnects Table 3-25 lists the structure of a 802.3X FC packet. Table 3-25. 802.3X Packet Format DA 01_80_C2_00_00_01 (6 bytes) SA Port MAC address (6 bytes) Type 0x8808 (2 bytes) Op-code 0x0001 (2 bytes) Time XXXX (2 bytes) Pad 42 bytes CRC 4 bytes 3.7.5.1.2 Operation and Rules The I210 operates in Link FC. • Link FC is enabled by the RFCE bit in the CTRL register.
Interconnects—Ethernet Controller I210 3.7.5.2 PAUSE and MAC Control Frames Forwarding Two bits in the Receive Control register, control forwarding of PAUSE and MAC control frames to the host. These bits are Discard PAUSE Frames (DPF) and Pass MAC Control Frames (PMCF): • The DPF bit controls forwarding of PAUSE packets to the host. • The PMCF bit controls forwarding of non-PAUSE packets to the host. Note: When flow control reception is disabled (CTRL.
Ethernet Controller I210 —Interconnects The I210 sends a PAUSE frame when Rx packet buffer is full above the high threshold defined in the Flow Control Receive Threshold High (FCRT0.RTH) register field. When the threshold is reached, the I210 sends a PAUSE frame with its pause time field equal to FCTTV. The threshold should be large enough to overcome the worst case latency from the time that crossing the threshold is sensed until packets are not received from the link partner.
Interconnects—Ethernet Controller I210 Note: The Flow Control Refresh Threshold mechanism does not work in the case of softwareinitiated flow control. Therefore, it is the software’s responsibility to re-generate PAUSE frames before expiration of the pause counter at the other partner's end. The state of the CTRL.TFCE bit or the negotiated flow control configuration does not affect software generated PAUSE frame transmission.
Ethernet Controller I210 —Interconnects 3 SerDes Interface 1 PCIe Packet Buffer and DMA MAC SerDes/ SGMII GMII Internal PHY 1GbT 2 4 Figure 3-12. I210 Loopback Modes In addition, The I210’s copper PHY support a far end loopback mode, where incoming traffic is reflected at the PHy level onto the transmit wires. This mode is entered by setting bit 14 in PHY register Page 2, Register 21. 3.7.6.
Interconnects—Ethernet Controller I210 — Set speed using bits 6 and 13. Register values should be: • For 10 Mb/s 0x4100 • For 100 Mb/s 0x6100 • For 1000 Mb/s 0x4140 — Use bits 2:0 in PHYREG 2,21 to control the link speed in MDI loopback — reset the PHY – in PHYREG 0,0 Set Copper Reset bit (bit 15) — In PHYREG 0,0 Set loopback bit (bit 14) 3.7.6.
Ethernet Controller I210 —Interconnects 3.7.6.5.1 Setting the I210 Internal PHY to External Loopback Mode For 1000 Mb/s, the following procedure should be used to put the I210 internal PHY into external loopback mode: • Set Link mode to PHY: CTRL_EXT.
Interconnects—Ethernet Controller I210 3.7.7 Energy Efficient Ethernet (EEE) Energy Efficient Ethernet (EEE) Low Power Idle (LPI) mode defined in IEEE802.3az optionally enables power saving by switching off part of the I210 functionality when no data needs to be transmitted or/ and received. The decision as to whether or not the I210 transmit path should enter LPI mode or exit LPL mode is done according to transmit needs.
Ethernet Controller I210 —Interconnects 3.7.7.1 Conditions to Enter EEE Tx LPI In the transmit direction when the network interface is internal copper PHY (CTRL_EXT.LINK_MODE = 00b), entry into to EEE LPI mode of operation is triggered when one of the following conditions exist: 1. No transmission is pending, management does not need to transmit, the internal transmit buffer is empty, and EEER.TX_LPI_EN is set to 1b. 2. If the EEER.TX_LPI_EN and EEER.
Interconnects—Ethernet Controller I210 3.7.7.3 EEE Auto-Negotiation Auto-negotiation provides the capability to negotiate EEE capabilities with the link partner using the next page mechanism defined in IEEE802.3 Annex 28C. IEEE802.3 auto-negotiation is performed at power up, on command from software, upon detection of a PHY error or following link re-connection. During the link establishment process, both link partners indicate their EEE capabilities via the IEEE802.3 auto-negotiation process.
Ethernet Controller I210 —Interconnects Note: If link is disconnected or auto-negotiation is re-initiated, then the LTRC.EEEMS_EN bit is cleared by hardware. The bit should be set to 1b by software following re-execution of an EEE LLDP negotiation. Figure 3-15 shows the format of the EEE TLV, meaning of the various TLV parameters can be found in IEEE802.3az clause 78 and clause 79. Figure 3-15. EEE LLDP TLV 3.7.7.
Interconnects—Ethernet Controller I210 6. Set the LTRC.EEEMS_EN bit to 1b, to enable sending an updated PCIe LTR message when detecting a link partner entry into EEE Rx LPI state. Notes: 1. The LTRC.EEEMS_EN bit is cleared following link disconnect or auto-negotiation and should be set to 1b by software following EEE LLDP re-negotiation. 2. The I210 waits for at least 1 second following auto-negotiation (due to reset, link disconnect, or link speed change) and link-up indication (STATUS.
Ethernet Controller I210 —Interconnects • Forced operation Auto-negotiation is the only method allowed by the 802.3ab standard for establishing a 1000BASE-T link, although forced operation could be used for test purposes. For 10/100 links, any of the three methods can be used. The following sections discuss each in greater detail. Figure 3-16 provides an overview of link establishment. First the PHY checks if auto-negotiation is enabled.
Interconnects—Ethernet Controller I210 The PHY does not falsely establish link with a partner operating at a different speed. For example, the PHY does not establish a 1 Gb/s or 10 Mb/s link with a 100 Mb/s link partner. When the PHY is first powered on, reset, or encounters a link down state; it must determine the line speed and operating conditions to use for the network link.
Ethernet Controller I210 —Interconnects 3.7.8.1.3 Auto Negotiation The PHY supports the IEEE 802.3u auto-negotiation scheme with next page capability. Next page exchange uses Register 7 to send information and Register 8 to receive them. Next page exchange can only occur if both ends of the link advertise their ability to exchange next pages. 3.7.8.1.4 Parallel Detection Parallel detection can only be used to establish 10 and 100 Mb/s links.
Interconnects—Ethernet Controller I210 MDI (DTE/NIC) R TX A J RX 5 - B 4 Phy TX C RX D MDIX (Switch) Flat Cable 1 2 TX 3 6 RX 4 5 TX 7 8 RX CROSS(1:0) = 00 1 RX 2 3 TX 6 4 RX 5 7 TX 8 R J A 4 B 5 RX C TX D RX TX CROSS(1:0) = 01 Figure 3-17. Cross-Over Function 3.7.8.1.6 10/100 MB/s Mismatch Resolution It is a common occurrence that a link partner (such as a switch) is configured for forced full-duplex (FDX) 10/100 Mb/s operation.
Ethernet Controller I210 —Interconnects Either side indicates completion of the training phase to its link partner by changing the encoding of the idle symbols it transmits. When both sides so indicate, the link is up. Each side continues sending idle symbols each time it has no data to transmit. The link is maintained as long as valid idle, data, or carrier extension symbols are received. 3.7.8.1.7.
Interconnects—Ethernet Controller I210 3.7.8.3 Flow Control Flow control is a function that is described in Clause 31 of the IEEE 802.3 standard. It enables congested nodes to pause traffic. Flow control is essentially a MAC-to-MAC function. MACs indicate their ability to implement flow control during auto-negotiation. This ability is communicated through two bits in the auto-negotiation registers (PHYREG 0,4.10 and PHYREG 0,4.11).
Ethernet Controller I210 —Interconnects 3.7.8.5.1 Power Down via the PHY Register The PHY can be powered down using the control bit found in PHYREG 0,0.11. This bit powers down a significant portion of the port but clocks to the register section remain active. This enables the PHY management interface to remain active during register power down. The power down bit is active high. When the PHY exits software power-down (PHYREG 0,0.
Interconnects—Ethernet Controller I210 Table 3-32 lists link speed as function of power management state, link speed control, and GbE speed enabling: Table 3-32. Link Speed vs. Power State Power Management State Low Power Link Up (PHPM.1, PHPM.2) GbE Disable Bits 100M Disable Bit Disable 100 in non-D0a (PHPM.9) Disable 1000 in non-D0a (PHPM.3) 0b X X PHY negotiates to highest speed advertised (normal operation).
Ethernet Controller I210 —Interconnects 3.7.8.5.4.1 D0a State A power-managed link speed control lowers link speed (and power) when highest link performance is not required. When enabled (D0 Low Power Link Up mode), any link negotiation tries to establish a lowlink speed, starting with an initial advertisement defined by software. The D0LPLU configuration bit enables D0 Low Power Link Up.
Interconnects—Ethernet Controller I210 When the internal PHY is in SPD and detects link activity, it re-negotiates link speed based on the power state and the Low Power Link Up bits as defined by the PHPM.D0LPLU and PHPM.LPLU bits. Note: The PHY does not enter SPD unless auto-negotiation is enabled. While in SPD, the PHY powers down all circuits not required for detection of link activity.
Ethernet Controller I210 —Interconnects 3. Device off mode - Internal PHY can be disabled if the DEV_OFF_N pin is asserted. Since the PHY is shared between the LAN function and manageability, it might not be desirable to power down the PHY in Device Disable mode. The PHY_in_LAN_Disable Flash bit determines whether the PHY (and MAC) are powered down when the DEV_OFF_N pin is asserted. The default is to power down.
Interconnects—Ethernet Controller I210 M A C Interface 8 8 S ide - stream S cram bler / D escram bler Trellis V iterbi E ncoder/ D ecoder 4 DSP 4 ECHO, NEXT, FE X T C ancellers 4D P A M 5 E ncoder A G C , A /D , Tim ing R ecovery P ulse S haper, D A C , Filter H ybrid Line D river Line Interface Figure 3-18. 1000BASE-T Functions Overview 3.7.8.7.
Ethernet Controller I210 —Interconnects The scrambler is driven by a 33-bit Linear Feedback Shift Register (LFSR), which is randomly loaded at power up. The LFSR function used by the master differs from that used by the slave, giving each direction its own unique signature. The LFSR, in turn, generates twelve mutually uncorrelated outputs. Eight of these are used to randomize the inputs to the 4DPAM5 and Trellis encoders. The remaining four outputs randomize the sign of the 4DPAM5 outputs. 3.7.8.7.2.
Interconnects—Ethernet Controller I210 3.7.8.7.2.7 Low-Pass Filter To aid with EMI, this filter attenuates signal components more than 180 MHz. In 1000BASE-T, the fundamental symbol rate is 125 MHz. 3.7.8.7.2.8 Line Driver The line driver drives the 4DPAM5 waveforms onto the four twisted-pair channels (A, B, C, D), adding them onto the waveforms that are simultaneously being received from the link partner.
Ethernet Controller I210 —Interconnects 3.7.8.7.3 Receive Functions This section describes function blocks that are used when the PHY receives data from the twisted pair interface and passes it back to the MAC (see Figure 3-20). 3.7.8.7.3.1 Hybrid The hybrid subtracts the transmitted signal from the input signal, enabling the use of simple 100BASETX compatible magnetics. 3.7.8.7.3.
Interconnects—Ethernet Controller I210 3.7.8.7.3.7 Viterbi Decoder/Decision Feedback Equalizer (DFE) The Viterbi decoder generates clean 4DPAM5 symbols from the output of the DSP. The decoder includes a Trellis encoder identical to the one used by the transmitter. The Viterbi decoder simultaneously looks at the received data over several baud periods. For each baud period, it predicts whether the symbol received should be even or odd, and compares that to the actual symbol received.
Ethernet Controller I210 —Interconnects 3.7.8.7.3.14 Polarity Correction The PHY automatically detects and corrects for the condition where the receive signal (MDI_PLUS[0]/ MDI_MINUS[0]) is inverted. Reversed polarity is detected if eight inverted link pulses or four inverted end-of-frame markers are received consecutively. If link pulses or data are not received for 96-130 ms, the polarity state is reset to a non-inverted state.
Initialization—Ethernet Controller I210 4.0 Initialization 4.1 Power Up 4.1.1 Power-Up Sequence Figure 4-1 shows the power-up sequence from power ramp up and to when the I210 is ready to accept host commands.
Ethernet Controller I210 —Initialization 4.1.2 Power-Up Timing Diagram Power txog 1 Xosc tppg 2 Power‐On‐Reset (internal) tPVPGL PCIe reference clock 7 tPWRGD‐CLK 6 PERST# 8 3 tee Auto Read Flash Load Ext. Conf. Auto Read Ext. Conf. tpgtrn 4 PHY State tee 9 P o w e re d ‐ d o w n tpgres tpgcfg A c ti v e / D o w n 10 11 PCIe Link Up 12 13 L0 5 Manageability / Wake D‐State Dr Figure 4-2. Power-Up Timing Diagram Table 4-1.
Initialization—Ethernet Controller I210 4.2.1 Reset Sources The I210 reset sources are described in the sections that follow. 4.2.1.1 LAN_PWR_GOOD The I210 has an internal mechanism for sensing the power pins. Once power is up and stable, the I210 creates an internal reset. This reset acts as a master reset of the entire chip. It is level sensitive, and while it is zero holds all of the registers in reset. LAN_PWR_GOOD is interpreted to be an indication that device power supplies are all stable.
Ethernet Controller I210 —Initialization A FLR reset to a function resets all the queues, interrupts, and statistics registers attached to the function. It also resets PCIe read/write configuration bits as well as disables transmit and receive flows for the queues allocated to the function.
Initialization—Ethernet Controller I210 4.3.1.2 Force TCO This reset is generated when manageability logic is enabled and the MC detects that the I210 does not receive or transmit data correctly. Force TCO reset is enabled if the Reset on Force TCO bit in the Management Control Flash word is set 1b. Table 4-3 describes affects of TCO reset on the I210 functionality. Force TCO reset is generated in pass through mode when the MC issues a Force TCO command with bit 1 set and the previous conditions exist.
Ethernet Controller I210 —Initialization • Set the SWSM.SWESMBI bit. • Read SWSM. • If SWSM.SWESMBI was successfully set (semaphore was acquired); otherwise, go back to step a. • Clear the bit in SW_FW_SYNC that control the software ownership of the resource to indicate this resource is free. • Release ownership of the software/firmware semaphore by clearing the SWSM.SWESMBI bit. 7. Wait for the CFG_DONE bit (EEMNGCTL.CFG_DONE0). 8. Take ownership of the relevant PHY using the following flow: a.
Initialization—Ethernet Controller I210 Table 4-2. I210 Reset Affects - Common Resets (Continued) FW Reset Reset Activation LAN_PWR_GOOD PE_ RST_N In-Band PCIe Reset MAC, PCS, Auto Negotiation and Other Port Related Logic X X X DMA X X X Functions Queue Enable X X X Function interrupt and Statistics Registers X X X Wake Up (PM) Context X 7. Wake Up Control Register X 8. Wake Up Status Registers X 9. Manageability Control Registers X MMS Unit X Notes 10.
Ethernet Controller I210 —Initialization Table 4-3. I210 Reset Affects - Other Resets (Continued) Reset Activation D3hotD0 FLR Flash Request X X PHY/SerDes PHY X X Port SW Reset (CTRL.RST) Force TCO EE Reset PHY Reset Notes 14. X X 2. Strapping Pins Notes: 1. If AUX_POWER = 0b the Wakeup Context is reset (PME_Status and PME_En bits should be 0b at reset if the I210 does not support PME from D3cold). 2. The MMS unit must configure the PHY after any PHY reset. 3.
Initialization—Ethernet Controller I210 The shadow copies of these bits in the Wakeup Control register are treated identically. 8. Refers to bits in the Wake Up Control register that are not part of the Wake-Up Context (the PME_En and PME_Status bits). 9. The Wake Up Status registers include the following: a. Wake Up Status register b. Wake Up Packet Length. c. Wake Up Packet Memory. 10. The Manageability Control registers refer to the following registers: a. MANC 0x5820 b.
Ethernet Controller I210 —Initialization a. The Tx packet buffers b. The Rx packet buffers 14. Includes EEC.REQ, EEC.GNT, FLA.REQ and FLA.GNT fields. 15. The following DMA registers are cleared only by LAN_PWR_GOOD, PCIe Reset or CTRL.DEV_RST: DMCTLX, DTPARS, DRPARS and DDPARS. 16. CTRL.DEV_RST assertion causes read of function related sections. 4.3.
Initialization—Ethernet Controller I210 4.4 Device and Function Disable 4.4.1 General For a LAN on Motherboard (LOM) design, it might be desirable for the system to provide BIOS-setup capability for selectively enabling or disabling LAN functions. It enables the end-user more control over system resource-management and avoid conflicts with add-in NIC solutions. The I210 provides support for selectively enabling or disabling one or more LAN device(s) in the system.
Ethernet Controller I210 —Initialization 4.4.4 BIOS Handling of Device Disable 4.4.4.1 Sequence for Entering the (Static) Device Off State 1. BIOS recognizes that the entire device should be disabled. The Device Off Enable Flash bit in word 0x1E should be set to 1b. a. In order to shut down the PHY together with the rest of the device, the PHY_in_LAN_Disable Flash bit (refer to Section 6.2.21) should be set to 1b. 2. BIOS asserts the DEV_OFF_N pin (device is on and not in PCIe reset). 3.
Initialization—Ethernet Controller I210 4.5.3 Initialization Sequence The following sequence of commands is typically issued to the device by the software device driver in order to initialize the I210 to normal operation. The major initialization steps are: • Disable Interrupts - see Interrupts during initialization. • Issue Global Reset and perform General Configuration - see Global Reset and General Configuration. • Setup the PHY and the link - see Link Setup Mechanisms and Control/Status Bit Summary.
Ethernet Controller I210 —Initialization The receive buffer size is controlled by RXPBSIZE.Rxpbsize register field. Refer to Section 4.5.9 for its setting rules. If DMA coalescing is enabled, to avoid packet loss, the FCRTC.RTH_Coal field should also be programmed to a value equal to at least a single maximum packet size below the receive buffer size (a value equal or less than FCRTH0.RTH + max size packet). 4.5.7 Link Setup Mechanisms and Control/Status Bit Summary The CTRL_EXT.
Initialization—Ethernet Controller I210 CTRL.RFCE Must be programmed by software after reading capabilities from PHY registers and resolving the desired flow control setting. CTRL.TFCE Must be programmed by software after reading capabilities from PHY registers and resolving the desired flow control setting. CTRL.SPEED Set by software based on reading PHY status register after PHY has autonegotiated a successful link-up. STATUS.FD Reflects the MAC forced duplex setting written to CTRL.FD. STATUS.
Ethernet Controller I210 —Initialization STATUS.SPEED Reflects 1000Mb/s speed, reporting fixed value of 10b. PCS_LCTL.FSD Must be zero. PCS_LCTL.Force Flow Control Must be zero1. PCS_LCTL.FSV Must be set to 10b. Only 1000 Mb/s is supported in SerDes mode. PCS_LCTL.FDV Ignored; duplex is set by priority resolution of PCS_ANDV and PCS_LPAB. PCS_LCTL.AN TIMEOUT EN Must be 1b to enable auto-negotiation time-out. CONNSW.
Initialization—Ethernet Controller I210 CTRL.RFCE Must be programmed by software after reading capabilities from external PHY registers and resolving the desired setting. CTRL.TFCE Must be programmed by software after reading capabilities from external PHY registers and resolving the desired setting. CTRL.SPEED Ignored; speed setting is established from SGMII's internal indication to the MAC after SGMII PHY has auto-negotiated a successful link-up. STATUS.
Ethernet Controller I210 —Initialization 4.5.8 Initialization of Statistics Statistics registers are hardware-initialized to values as detailed in each particular register's description. The initialization of these registers begins upon transition to D0active power state (when internal registers become accessible, as enabled by setting the Memory Access Enable bit of the PCIe Command register), and is guaranteed to be completed within 1 s of this transition.
Initialization—Ethernet Controller I210 4.5.9.1 Initialize the Receive Control Register To properly receive packets the receiver should be enabled by setting RCTL.RXEN. This should be done only after all other setup is accomplished. If software uses the Receive Descriptor Minimum Threshold Interrupt, that value should be set. 4.5.9.
Ethernet Controller I210 —Initialization • If needed, set TDWBAL/TWDBAH to enable head write back. • Enable the queue using TXDCTL.ENABLE (queue zero is enabled by default). • Poll the TXDCTL register until the ENABLE bit is set. Note: The tail register of the queue (TDT[n]) should not be bumped until the queue is enabled. Enable transmit path by setting TCTL.EN. This should be done only after all other settings are done. 4.5.10.
Initialization—Ethernet Controller I210 If the factory MAC address was restored by the internal firmware, the FWSM.Factory MAC address restored bit is set. If the value at word 0x37 is valid, but the MAC addresses in the alternate MAC structure are not valid (0xFFFFFFFF), the regular MAC address is backed up in the alternate MAC structure. The I210 supports replacing the MAC address with a BIOS CLP interface. 4.
Ethernet Controller I210 —Initialization b. If one of the bits is set (firmware or other software owns the resource), software tries again later. 4. Release ownership of the software/software semaphore and the software/firmware semaphore by clearing SWSM.SMBI and SWSM.SWESMBI bits. 5. At this stage, the shared resources is owned by the software device driver and it might access it. The SWSM and SW_FW_SYNC registers can now be used to take ownership of another shared resources.
Power Management—Ethernet Controller I210 5.0 Power Management This section describes how power management is implemented in the I210. The I210 supports the Advanced Configuration and Power Interface (ACPI) specification as well as Advanced Power Management (APM). Power management can be disabled via the power management bit in the Initialization Control Word 1 Flash word (see Section 6.2.2), which is loaded during power-up reset. Even when disabled, the power management register set is still present.
Ethernet Controller I210 —Power Management • L2/L3 Ready: This link state prepares the PCIe link for the removal of power and clock. The I210 is in the D3hot state and is preparing to enter D3cold. The power-saving opportunities for this state include, but are not limited to, clock gating of all PCIe architecture logic, shutdown of the PLL, and shutdown of all transceiver circuitry. • L2: This link state is intended to comprehend D3cold with auxiliary power support.
Power Management—Ethernet Controller I210 5.2.1 D0 Uninitialized State (D0u) The D0u state is an architectural low-power state. When entering D0u, the I210: • Asserts a reset to the PHY while the Flash is being read. • Disables wake up. However APM wake up is enabled (See additional information in Section 5.6.1), if all of the following register bits are set: — The WUC.APME bit is set to 1b. — The WUC.APMPME bit or the PMCSR.PME_en bits are set to 1b. — The WUC.EN_APM_D0 bit is set to 1b. 5.2.1.
Ethernet Controller I210 —Power Management 5.2.3 D3 State (PCI-PM D3hot) The I210 transitions to D3 when the system writes a 11b to the Power State field of the Power Management Control/Status Register (PMCSR). Any wake-up filter settings that were enabled before entering this state are maintained. If the PMCSR.
Power Management—Ethernet Controller I210 In order to reduce power consumption, if the link is still needed for manageability, wake-up or proxying functionality, the PHY can auto-negotiate to a lower link speed on D3 entry (See Section 3.7.8.5.4). 5.2.3.2 Exit from D3 State A D3 state is followed by either a D0u state (in preparation for a D0a state) or by a transition to Dr state (PCI-PM D3cold state).
Ethernet Controller I210 —Power Management In the event of a PCIe Master disable (Configuration Command register.BME set to 0b) or LAN port disabled or if the function is moved into D3 state during a DMA access, the I210 generates an internal reset to the function and stops all DMA accesses and interrupts. Following a move to normal operating mode, the software device driver should re-initialize the receive and transmit queues of the relevant port.
Power Management—Ethernet Controller I210 Once the I210 enters Dr state on power-up, the Flash is read. If the Flash contents determine that the conditions to enter Dr disable mode are met, the I210 then enters this mode (assuming that PCIe PE_RST_N is still asserted). The I210 exits Dr disable mode when Dr state is exited (See Figure 5-1 for conditions to exit Dr state). Refer to Section 5.2.6 for details about the static/dynamic device off states built on Dr Disable Mode. 5.2.4.
Ethernet Controller I210 —Power Management 5.2.5 Link Disconnect In any of D0u, D0a, D3, or Dr power states, the I210 enters a link-disconnect state if it detects a linkdisconnect condition on the Ethernet link. Note that the link-disconnect state in the internal PHY is invisible to software (other than the PHPM.Link Energy Detect bit state). In particular, while in D0 state, software might be able to access any of the I210 registers as in a link-connect state. 5.2.
Power Management—Ethernet Controller I210 The I210 exceeds the allocated auxiliary power in some configurations. The I210 must therefore be configured to meet the previously mentioned requirements. To do so, the I210 implements three Flash bits to disable operation in certain cases: 1. The PHPM.Disable_1000 PHY register bit disables 1000 Mb/s operation under all conditions. 2. The PHPM.Disable 1000 in non-D0a PHY CSR bit disables 1000 Mb/s operation in non-D0a states1. If PHPM.
Ethernet Controller I210 —Power Management Internal Power On Reset assertion L0s L3 Dr PERST# deassertion PERST# assertion L2 D0u L0 L1 Write 11b to Power State Enable master access PERST# assertion Write 00b to Power State & (BME = 0 OR No_Soft_Reset = 0) L1 PERST# assertion L0s Write 11b to Power State D0a L0 D3 Figure 5-2.
Power Management—Ethernet Controller I210 • L0s Acceptable Latency (as published in the Endpoint L0s Acceptable Latency field of the Device Capabilities Register) is loaded from Flash. The I210 transitions the link into L0s state once the PCIe link has been idle for a period of time defined in the Latency_To_Enter_L0s field in the CSR Auto Configuration Power-Up NVM section (see Section 6.3).
Ethernet Controller I210 —Power Management 5.5.
Power Management—Ethernet Controller I210 5.5.2 Transition from D0a to D3 and Back Without PE_RST_N PCIe Reference Clock PE_RSTn D0 Write 3 2 Reading Flash PHY Reset PCIe Link td0mem tee Memory Access Enable 6 Read Flash 5 D3 write 7 1 L0 L0 L1 4 Wake Up Enabled PHY Power State DState Any mode full D0a APM /SMBus powe r‐m a na g e d D3 powe r‐ma na g e d D 0u Figure 5-4. Transition from D0a to D3 and Back Without PE_RST_N Table 5-3.
Ethernet Controller I210 —Power Management 5.5.3 Transition From D0a to D3 and Back With PE_RST_N 4a PCIe Reference Clock tclkpg PE_RSTn 4b tPWRGD‐CLK tl2clk 6 tpgdl 3 tl2pg tppg‐clkint 7 Internal PCIe Clock (2.
Power Management—Ethernet Controller I210 5.5.4 Transition From D0a to Dr and Back Without Transition to D3 1 PCIe Reference Clock tclkpg tPWRGD‐CLK 3 PE_RSTn tpgdl tppg‐clkint 4 Internal PCIe Clock (2.5 GHz) 5 tclkpr Internal PwrGd (PLL) 6 tee 2 Reading Flash Read Flash 8 Reset to PHY (active low) tpgtrn 9 PCIe Link tpgcfg tpgres 11 10 L0 12 L0 7 Wake Up Enabled Any mode PHY Power State DState full APM/SMBus power‐managed D0a full Dr D0u Figure 5-6.
Ethernet Controller I210 —Power Management 5.5.5 Timing Requirements The I210 requires the following start-up and power state transitions. Parameter Description Min. Max. Notes txog Xosc stable from power stable tPE_RST-CLK PCIe clock valid to PCIe power good 100 s - According to PCIe spec. tPVPGL Power rails stable to PCIe PE_RST active 100 ms - According to PCIe spec. Tpgcfg External PE_RST signal to first configuration cycle. 100 ms According to PCIe spec.
Power Management—Ethernet Controller I210 5.6.1 Advanced Power Management Wake Up Advanced Power Management Wake Up or APM Wakeup (also known as Wake on LAN) is a feature that existed in earlier 10/100 Mb/s NICs. This functionality was designed to receive a broadcast or unicast packet with an explicit data pattern, and then assert a subsequent signal to wake up the system. This was accomplished by using a special signal that ran across a cable to a defined connector on the motherboard.
Ethernet Controller I210 —Power Management Activating PCIe power management wake up requires the following: • System software writes at configuration time a 1b to the PCI PMCSR.PME_En bit. • Software device driver clears all pending wake-up status bits in the Wake Up Status (WUS) register.
Power Management—Ethernet Controller I210 Table 5-6.
Ethernet Controller I210 —Power Management — IPv6 MLD queries, with the Solicited-node Multicast Address placed in the IPv6 destination address field of the IPv6 NS packets that are off-loaded by the I210 (as defined in RFC 2710 and RFC 3810). The MLDv2 Multicast Listener Report messages returned by firmware to MLDv2 Multicast Listener Query messages which concern the device, contain a Multicast Address Record for each configured Solicited IPv6 addresses (up to 2).
Power Management—Ethernet Controller I210 13. Release management Host interface semaphore (SW_FW_SYNC.SW_MNG_SM register bit) using the flow defined in Section 4.6.2. 14. Verify that a firmware reset was not initiated during the proxying configuration process by reading the FWSTS.FWRI firmware reset indication bit. If a firmware reset was initiated. Return to step 1. 15. Set WUC.PPROXYE bit to 1b and enable entry into D3 low power state. 16.
Ethernet Controller I210 —Power Management — If a firmware reset was issued as reported in the FWSTS.FWRI bit, the software device driver should clear the bit and then re-initialize the protocol offload list. 7. Write proxying information in the shared RAM interface located in addresses 0x8800-0x8EFF using the format defined in Section 10.8.2.4.2. All addresses should be placed in networking order. 8. Once information is written into the shared RAM, software should set the HICR.C bit to 1b. 9.
Power Management—Ethernet Controller I210 The mDNS proxy architecture is based on the receive filter and the management controller, the filter is responsible to parse and filter incoming packets and pass the relevant packets to the management controller or wake the system if a packet matches one of the wake up filters. The host driver is responsible to properly configure the filter.
Ethernet Controller I210 —Power Management Table 5-7. mDNS Offload Configuration Frame Type ARP Request Address/Protocol Why Needed I210 Implementation Filter Local IPv4 address/ARP Maintain IPv4 connectivity PROXYFC.ARP / PROXYFC.ARP_Directed IGMPv2 224.0.0.251/IGMP Maintain presence in mDNS group PROXYFCEX.IGMP / PROXYFCEX.IGMP_mDirected Multicast mDNS 224.0.0.251/UDP/5353 FF02::FB/UDP/5353 Listen to multicast mDNS queries and respond when proper PROXYFCEX.mDNS / PROXYFCEX.
Power Management—Ethernet Controller I210 The I210 exits DMA coalescing once the conditions defined in Section 5.8.3, to exit DMA coalescing, exist. 5.8.1 DMA Coalescing Activation To activate DMA coalescing functionality software driver should program the following fields: 1. DMACR.DMACTHR field to set the receive threshold that causes move out of DMA coalescing operating mode. Receive watermark programmed should take into account latency tolerance reported (See Section 5.
Ethernet Controller I210 —Power Management 8. DOBFFCTL.OBFFTHR field to set the low receive threshold that causes move out of DMA coalescing operating mode when the PCIe is in OBFF or OBFF Active states. Receive watermark programmed must be lower than DMACR.DMACTHR. 9. DMCTLX.EN_MNG_IND bit should be set to 1b to enable management indication impact on DMA Coalescing and OBFF operating modes. This bit also enables DMA coalescing and OBFF impact on MCTP over PCIe traffic. 10. DMCMNGTH.
Power Management—Ethernet Controller I210 5.8.3 Conditions to Exit DMA Coalescing 5.8.3.1 Exiting DMA Coalescing When the I210 is in DMA coalescing operating mode, DMA coalescing mode is exited when one of the following events occurs: 1. Amount of data in the internal receive buffer passed the DMACR.DMACTHR threshold or when OBFF is enabled and in OBFF or “OBFF Active” states, the amount of data in internal receive buffer passed the DOBFFCTL.OBFFTHR threshold. 2.
Ethernet Controller I210 —Power Management In systems that don’t support OBFF, asynchronous device activity prevents optimal power management of memory, CPU, and other Root Complex (RC) internal circuitry because device activity tends to be misaligned with respect to other devices and with respect to the natural activity of the system. The PCIe OBFF mechanism implemented in the I210 enables synchronizing device activity and optimizing system power management.
Power Management—Ethernet Controller I210 3. If the I210 reported following PCIe link-up latency tolerance requirements with any requirement bit set and the LTR Mechanism Enable bit in the PCIe configuration space is cleared, the I210 sends a new LTR message with all the requirement bits clear. 4. The I210 sends a LTR message with the value placed in the LTRMAXV register when either one of following conditions exist: a. Software set the LTRC.LTR_MAX register bit. b.
Reset Ethernet Controller I210 —Power Management No LTR Enabled ? Send LTR message with Valid bits cleared No Yes Valid bits cleared in previous LTR message? Yes Yes Port disabled or disconnected? Send LTR = Max Yes A No Max value different than last submitted LTR value? No EEE RX LPI or Send Max LTR bit set? Yes No A Min value different than last submitted LTR Value or Min LTR bit set? Yes Send LTR = Min Figure 5-7.
Power Management—Ethernet Controller I210 5.10.2 Latency Tolerance Reporting The PCIe function can request to generate a minimum value LTR, a maximum value LTR, and a LTR message with the requirement bits cleared.
Ethernet Controller I210 —Power Management 5.10.2.2 Conditions for Generating LTR Message with Maximum LTR Value When LTR messaging is enabled and conditions to send a LTR message with valid bits cleared do not exist, the I210 functions send a maximum value LTR message, with the values programmed in the LTRMAXV register in the following cases: 1. Following a software write of 1b to the LTRC.
Flash Map—Ethernet Controller I210 6.0 Flash Map 6.1 Flash General Map Table 6-1 lists the Flash map used by the I210. This table lists common modules for the Flash including: hardware pointers, software and firmware. Blocks are detailed in the following sections. All addresses and pointers in Table 6-1 are absolute in word units. A detailed list of Flashwords loaded by hardware following power up, hardware reset or software generated resets (CTRL.RST, CTRL_EXT.EE_RST or CTRL.
Ethernet Controller I210 —Flash Map Flash Word Offsets Used By/In High Byte Low Byte 0x15 HW PCIe Completion Timeout Configuration (Word 0x15) - Section 6.2.12 0x16 HW MSI-X Configuration (Word 0x16) - Section 6.2.13 0x17 HW Software Reset CSR Auto Configuration Pointer (Offset 0x17) - Section 6.3 RO to Host RO pointer RO module 0x18 HW PCIe Init Configuration 1 (Word 0x18) - Section 6.2.14 0x19 HW PCIe Init Configuration 2 Word (Word 0x19) - Section 6.2.
Flash Map—Ethernet Controller I210 Flash Word Offsets Used By/In High Byte Low Byte 0x41 SW Free Provisioning Area Size, expressed in 4KB sectors. Default is 0x3D. Section 6.9 0x42 SW Image Unique ID (Words 0x42, 0x43) - Section 6.8.10 RO to Host 0x43 SW Image Unique ID (Words 0x42, 0x43) - Section 6.8.10 0x44:0x4F SW Reserved 0x50 FW RO Updates Version (Word 0x50) - Section 6.6 RO word 0x51 FW Pointer to Firmware module (Word 0x51) - Section 6.
Ethernet Controller I210 —Flash Map Bit 15 14 13 12 Name iNVM GPAR_EN LTR_EN VPD_EN Default HW Mode Description 0b 0b1 Global Parity Enable Enables parity checking of all the I210 memories. 0b = Disable parity check 1b = Enable parity check according to the per RAM parity enable bits. Loaded to the PCIEERRCTL register (refer to Section 8.24.4) only at LAN_PWR_GOOD events.
Flash Map—Ethernet Controller I210 6.2.3 Subsystem ID (Word 0x0B) If the Load Subsystem IDs in Initialization Control Word 1 Flash word is set, the Subsystem ID word in the Common section is read in to initialize the PCIe Subsystem ID. Default value is 0x0 (refer to Section 9.3.14). 6.2.
Ethernet Controller I210 —Flash Map Bit Default HW Mode Name 0b Description Enable entry into EEE LPI on TX path. Refer to Section 8.25.12. 0b = Disable entry into EEE LPI on Tx path. 1b = Enable entry into EEE LPI on Tx path. 8 TX_LPI_EN 7 MAC Clock Gating Enable 0b 6 PHY Power Down Enable 1b When set, enables the internal PHY to enter a low-power state (refer to Section 3.7.8.5). This bit is mapped to CTRL_EXT[20] (refer to Section 8.2.3).
Flash Map—Ethernet Controller I210 4 Unprotect After Reset 0b When set, the Flash internal protection is removed after reset - operating the device in the non-secured mode. 3 SST Mode 0b When set, the device operates the Flash device pins as if it was an SST Flash part. Meaningful only when bit 8 is set or when the Flash part was not found in the Flash devices table embedded in the firmware image. 000b Flash Size.
Ethernet Controller I210 —Flash Map 6.2.11 PCIe L1 Exit Latencies (Word 0x14) Bits Default HW Mode Name Description 15 Reserved 1b Reserved. 14:12 L1_Act_Acc_Latency 110b Loaded to the Endpoint L1 Acceptable Latency field in Device Capabilities in the PCIe Configuration registers at power up. 11:6 Reserved 0b Reserved. 5:3 L1 G1 Sep exit latency 100b L1 exit latency G1S. Loaded to Link Capabilities -> L1 Exit Latency at PCIe v2.1 (2.5GT/s) system in a separate clock setting.
Flash Map—Ethernet Controller I210 Bits Default HW Mode Name 11:6 Reserved Description 0b Reserved. 5:3 L0s G1 Sep Exit Latency 111b L0s Exit Latency G1S Loaded to L0s Exit Latency field in the Link Capabilities register in the PCIe Configuration registers in PCIe v2.1 (2.5GT/s) system at a separate clock setting. 2:0 L0s G1 Com Exit Latency 101b L0s Exit Latency G1C Loaded to L0s Exit Latency field in the Link Capabilities register in the PCIe Configuration registers in PCIe v2.1 (2.
Ethernet Controller I210 —Flash Map 6.2.16 PCIe Init Configuration 3 Word (Word 0x1A) This word is used to set defaults for some internal PCIe registers. Bit Default HW Mode Name 15:13 AER Capability Version 12 Cache_Lsize 11:10 GIO_Cap Description 0x2 AER Capability Version Number PCIe AER extended capability version number. Refer to Section 9.5.1.1. 0b Cache Line Size 0b = 64 bytes. 1b = 128 bytes.
Flash Map—Ethernet Controller I210 6.2.18 LED1 Configuration Defaults (Word 0x1C) These Flash words specify the hardware defaults for the LEDCTL register fields controlling the LED1 (ACTIVITY indication) output behavior. These words control the LED behavior of the LAN port. Bit 15:11 Name Reserved Default HW Mode Description 0x0 Reserved. 7 LED1 Blink 1b Initial value of LED1_BLINK field. 0b = Non-blinking. See Section 8.2.8 and Section 7.5.
Ethernet Controller I210 —Flash Map 6.2.20 LED0,2 Configuration Defaults (Word 0x1F) These Flash words specify the hardware defaults for the LEDCTL register fields controlling the LED (LINK_UP) and LED2 (LINK_100) output behaviors. These words control the LED behavior of the LAN port. Bit Name Default HW Mode Description 15 LED2 Blink 0b Initial value of LED2_BLINK field. 0b = Non-blinking. Refer to Section 8.2.8 and Section 7.5. 14 LED2 Invert 0b Initial value of LED2_IVRT field.
Flash Map—Ethernet Controller I210 Bit Name Default HW Mode Description Disables 1000 Mb/s and 100 Mb/s operation in non-D0a states (refer to Section 3.7.8.5.4). Sets default value of PHPM.Disable 100 bit in non-D0a mode. 12 Disable 100 in non-D0a 0b 11 Reserved 0b Reserved. 10 I2C_ON_SDP_EN 0b When set to 1b, SDP pins 0 and 2 operate as I2C pins controlled by the I2CCMD and I2CPARAMS registers set. Used to set the default value of CTRL_EXT.I2C over SDP Enabled. Refer to Section 8.2.3.
Ethernet Controller I210 —Flash Map 6.2.22 Bit 15:12 11 10 9 Functions Control (Word 0x21) Name Reserved NC-SI ARB Enable BAR32 PREFBAR Default HW Mode Description 0x0 Reserved. 0b NC-SI Hardware Arbitration Enable 0b = NCSI_ARB_IN and NCSI_ARB_OUT pads are not used. NCSI_ARB_IN is pulled up internally to provide stable input. 1b = NCSI_ARB_IN and NCSI_ARB_OUT pads are used. 1b Bit (loaded to the BARCTRL register) preserves the legacy 32-bit BAR mode when BAR32 is set.
Flash Map—Ethernet Controller I210 6.2.23 LAN Power Consumption (Word 0x22) Bit Name Default HW Mode Description 15:8 LAN D0 Power 0x0 The value in this field is reflected in the PCI Power Management Data Register of the PCIe function for D0 power consumption and dissipation (Data_Select = 0 or 4). Power is defined in 100 mW units. The power also includes the external logic required for the LAN function. Refer to Section 9.4.1.4.
Ethernet Controller I210 —Flash Map Bit Default HW Mode Name Description Initial value of Link Mode bits of the Extended Device Control (CTRL_EXT.LINK_MODE) register, specifying which link interface and protocol is used by the MAC. 00b = MAC operates with internal copper PHY (10/100/1000BASE-T). 01b = MAC and SerDes I/F operate in 1000BASE-KX mode. 10b = MAC and SerDes operate in SGMII mode. 11b = MAC and SerDes I/F operate in SerDes (1000BASE-BX) mode. See Section 8.2.3.
Flash Map—Ethernet Controller I210 6.2.26 PCIe Control 3 (Word 0x29) This word is used for programming PCIe functionality and function disable control. Bits 15 Default HW Mode Name Description When set to 1b, enables disabling the PCIe function by driving the SDP_1 pin to 0b (refer to Section 4.4.3). Note: The SDP_1 pin on the port is sampled on power up and during PCIe reset. en_pin_pcie_func_dis 0b Reserved 0b Reserved.
Ethernet Controller I210 —Flash Map 6.2.29 Bit Watchdog Configuration (Word 0x2E) Default HW Mode Name Description 15 Watchdog Enable 0b Enable Watchdog Interrupt. Refer to Section 8.14.1. Note: If this bit is set to 1b the value of Flash Watchdog Timeout field should be 2 or higher to avoid immediate generation of a watchdog interrupt. 14:11 Watchdog Timeout 0x2 Watchdog Timeout Period (in seconds). Refer to Section 8.14.1. Note: Loaded to 4 LSB bits of WDSTP.WD_Timeout field.
Flash Map—Ethernet Controller I210 6.3.1 SW Reset CSR Configuration Section Length - Offset 0x0 The section length word contains the length of the section in words. Note that section length count does not include the section length word and Block CRC8 word. Bits 15 Reserved 14:0 Section_length 6.3.2 Reserved 7:0 CRC8 Reserved 14:0 CSR_ADDR 6.3.5 Bits 15:0 6.4 CRC8 is computed over the module, header excluded (for example, starting from word offset 0x2 included).
Ethernet Controller I210 —Flash Map Table 6-3. PCIe Reset CSR Auto Configuration Structure Format Offset High Byte[15:8] Low Byte[7:0] Section 0x0 Section Length = 3*n (n – number of CSRs to configure) Section 6.4.1 0x1 Block CRC8 Section 6.4.2 0x2 CSR Address Section 6.4.3 0x3 Data LSB Section 6.4.4 Data MSB Section 6.4.5 0x4 … 3*n - 1 CSR Address Section 6.5.3 3*n Data LSB Section 6.5.4 3*n + 1 Data MSB Section 6.5.5 6.4.
Flash Map—Ethernet Controller I210 6.4.5 CSR Data MSB - (Offset 3*n + 1; [n = 1... Section Length]) Bits Default HW Mode Name 15:0 CSR_Data_MSB 6.5 Description CSR Data MSB. CSR Auto Configuration Power-Up Pointer (Offset 0x27) This word points to the CSR auto configuration power-up structure of the LAN that is read only following power up. Sections are loaded during HW auto-load as described in Section 3.3.1.2. If no CSR autoload is required, the word must be set to 0xFFFF.
Ethernet Controller I210 —Flash Map 6.5.3 CSR Address - (Offset 3*n - 1; [n = 1... Section Length]) Bits Name 15 Reserved 14:0 CSR_ADDR 6.5.4 CSR Address in Double Words (4 bytes). Name Default HW Mode CSR_Data_LSB 6.5.5 Description CSR Data LSB. CSR Data MSB - (Offset 3*n + 1; [n = 1... Section Length]) Bits 15:0 Description CSR Data LSB - (Offset 3*n; [n = 1... Section Length]) Bits 15:0 Default HW Mode Name Default HW Mode CSR_Data_MSB 6.6 Description CSR Data MSB.
Flash Map—Ethernet Controller I210 Table 6-5. Firmware Module Header Global Flash Word Offset Description 0xA NC-SI Configuration Pointer - Section 6.7.6 0xB Traffic Types Parameters pointer - Section 6.7.7 0xC OEM Flash Structure Pointer. 0xD Reserved. 0xE Reserved. 0xF PHY Configuration Pointer - Section 6.7.8 0x10 SVR/LVR Control Configuration Pointer - Section 6.7.9 6.7.1 Common Firmware Parameters – (Global MNG Offset 0x3) 6.7.1.
Ethernet Controller I210 —Flash Map Bits Name 3 Proxying Capable 2 OS2BMC Capable 1:0 Reserved 6.7.1.3 1b Description Reserved 0b = Disable Protocol Offload. 1b = Enable Protocol Offload. 0b = Disable. 1b = Enable. 11b Reserved. Common Firmware Parameters 2 – Offset 0x2 Bits 15:12 Default HW Mode Name Default HW Mode Description Reserved Reserved 11 Multi-Drop NC-SI 1b Multi-Drop NC-SI Topology. 0b = Point-to-point. 1b = Multi-drop (default).
Flash Map—Ethernet Controller I210 6.7.2.1 Bits 15:8 7:0 Section Header — Offset 0x0 Name Default HW Mode Description Block CRC8 CRC8 is computed over the module, header included (for example, starting from word offset 0x0 included) where CRC8 field was zeroed before the computing. Block Length Block Length in Words In the initial image the size of this section must be zero, but enough space should be left to enable all filters to be set up (up to offset 0x84).
Ethernet Controller I210 —Flash Map 6.7.2.6 LAN IPv4 Address 3; (MIPAF15) — Offset 0x07-0x08 Same structure as LAN IPv4 Address 0. These values are stored in the MIPAF[15] register (0x58EC). Refer to Section 8.22.9 for a description of this register. Note: This value is ignored if Enable ARP Response in LRXEN1 is set (Section 6.7.2.18). 6.7.2.7 LAN Ethernet MAC Address 0 LSB (MMAL0) — Offset 0x09 This word is loaded by firmware to the 16 LS bits of the MMAL[0] register. Refer to Section 8.22.
Flash Map—Ethernet Controller I210 6.7.2.13 LAN UDP/TCP Flexible Filter Ports 0 — 15; (MFUTP Registers) — Offset 0x15 - 0x34 The words depicted in Table 6-6 are loaded by Firmware to the MFUTP registers. Refer to Section 8.22.2 for a description of the register. Table 6-6. Offset MFUTP Flash Words Bits Description 0x15 15:0 LAN UDP/TCP Flexible Filter Value Port0 0x16 15:0 LAN UDP/TCP Port0 Modifier - see the following table.
Ethernet Controller I210 —Flash Map This table lists the port modifiers bits: Bits Name Default HW Mode Description 0 UDP Match if port is UDP. 1 TCP Match if port is TCP. 2 Source/Destination 0 = Compare destination port. 1 = Compare source port. 3:15 Reserved Reserved. 6.7.2.14 Reserved LAN VLAN Filter 0 - 7; (MAVTV Registers) — Offset 0x35 — 0x3C The words depicted in Table 6-6 are loaded by firmware to the MAVTV registers. Refer to Section 8.22.1 for a description of the register.
Flash Map—Ethernet Controller I210 6.7.2.17 LAN MANC Value MSB; (LMANC MSB) — Offset 0x40 The value in this Flash word is stored in the MSB word of the MANC register. Refer to Section 8.22.5 for a description of this register. Bits 15:11 Name Default HW Mode Description Reserved Reserved. 10 NET_TYPE 0b NET TYPE: 0b = Pass only un-tagged packets. 1b = Pass only VLAN tagged packets. Valid only if FIXED_NET_TYPE is set.
Ethernet Controller I210 —Flash Map 6.7.2.19 LAN Receive Enable 2; (LRXEN2) — Offset 0x42 Bits Name Default HW Mode Description 15:8 Receive Enable byte 14 0x0 Alert value. 7:0 Receive Enable byte 13 0x0 Interface data. 6.7.2.20 Reserved LAN MNGONLY LSB; (LMNGONLY LSB) - Offset 0x43 The value in this Flash word is stored in the LSB word of the MNGONLY register. Refer to Section 8.22.6 for a description of this register.
Flash Map—Ethernet Controller I210 6.7.2.24 Manageability Decision Filters Extend 0 LSB; (MDEF_EXT0 LSB) - Offset 0x47 The value in this Flash word is stored in the LSB word of the MDEF_EXT[0] register. Refer to Section 8.22.8 for a description of this register. Bits 15:0 Name Default HW Mode MDEFEXT0_L 6.7.2.25 Description Reserved Loaded to 16 LS bits of MDEF_EXT[0] register.
Ethernet Controller I210 —Flash Map 6.7.2.30 Note: ARP Response IPv4 Address 0 LSB; (ARP LSB) - Offset 0x69 This value is overrides the value in LAN IPv4 Address 3 (Section 6.7.2.6) if Enable ARP Response in LRXEN1 is set (Section 6.7.2.18). Bits Name Default HW Mode Description 15:0 ARP Response IPv4 Address 0, Byte 1 ARP Response IPv4 Address 0, Byte 1 (firmware use). 7:0 ARP Response IPv4 Address 0, Byte 0 ARP Response IPv4 Address 0, Byte 0 (firmware use). 6.7.2.
Flash Map—Ethernet Controller I210 Bits Name Default HW Mode Description 15:8 LAN IPv6 Address 0 Byte 5 LAN IPv6 Address 0 Byte 5. 7:0 LAN IPv6 Address 0 Byte 4 LAN IPv6 Address 0 Byte 4. 6.7.2.35 Reserved LAN IPv6 Address 0 MSB; (MIPAF1 MSB) - Offset 0x6E This value is stored in the MIPAF[1] register (0x58B4). Refer to Section 8.22.9 for a description of this register. Bits Name Default HW Mode Description 15:8 LAN IPv6 Address 0 Byte 7 LAN IPv6 Address 0 Byte 7.
Ethernet Controller I210 —Flash Map 6.7.2.39 LAN IPv6 Address 0 MSB; (MIPAF3 MSB) - Offset 0x72 This value is stored in the MIPAF[3] register (0x58BC). Refer to Section 8.22.9 for a description of this register. Bits Default HW Mode Name Description 15:8 LAN IPv6 Address 0 Byte 15 LAN IPv6 Address 0 Byte 15. 7:0 LAN IPv6 Address 0 Byte 14 LAN IPv6 Address 0 Byte 14. 6.7.2.40 Reserved LAN IPv6 Address 1; MIPAF (Offset 0x73:0x7A) Same structure as LAN IPv6 Address 0.
Flash Map—Ethernet Controller I210 6.7.3.1 Section Header — Offset 0x0 Bits Name 15:8 Block CRC8 7:0 Block Length 6.7.3.2 7:0 6.7.3.3 Name Reserved Max Fragment Size CRC8 is computed over the module, header included (for example, starting from word offset 0x0 included) where CRC8 field was zeroed before the computing. 0x15 Section length in words. Default HW Mode Description 0x00 Reserved. 0x20 SMBus Maximum Fragment Size (bytes) Note: Value should be in the 32 to 240 byte range.
Ethernet Controller I210 —Flash Map 6.7.3.4 SMBus Slave Addresses — Offset 0x03 Bits Name Default HW Mode Description 15:8 Reserved 0b 7:1 SMBus 0 Slave Address 0x49 SMBus 0 slave address. 0 Reserved 0b Reserved. 6.7.3.5 Bits 15:0 6.7.3.6 6.7.3.7 Name Reserved Default HW Mode 0x0 Description Name Reserved Reserved. Default HW Mode 0x0 Description Reserved Description Reserved Reserved.
Flash Map—Ethernet Controller I210 6.7.3.8 NC-SI Configuration 2 - Offset 0x07 Bits Name Default HW Mode Description 0b = Read from Flash. 1b = Read from SDP. 15 Read NCSI Package ID from SDP 14:4 Reserved Reserved. Max XOFF Renewal NC-SI Flow Control MAX XOFF Renewal (# of XOFF renewals allowed). 0x0 = Disabled. Unlimited number of XOFF frames can be sent. 0x1 = Up to 2 consecutive XOFFs frames can be sent by the I210. 0x2 = Up to 3 consecutive XOFFs frames can be sent by the I210.
Ethernet Controller I210 —Flash Map 6.7.3.13 Bits 15:0 Name Bits Bits 15:8 7:0 224 Reserved Default HW Mode Description Reserved Should contain the same value as the factory station MAC address. OEM IANA (Offset 0x11) Name OEM IANA Number 6.7.3.17 Description Byte 9 & 10 of UUID as defined in DSP0236. Node Bits 15:0 Default HW Mode MCTP UUID - Node (Offset 0x0E-0x10) Name 6.7.3.16 Reserved Byte 7 & 8 of UUID as defined in DSP0236.
Flash Map—Ethernet Controller I210 6.7.3.18 Bits 15:7 6 5:0 Name No Simplified MCTP 0x0 If set, only SOM and EOM bits are used for the re-assembly process. Relevant only in SMBus mode. No Reserved Reserved. MCTP Rate Limiter Config 1 (Offset 0x14) Name MCTP Rate Default HW Mode Description 0x9C40 Defines the number of cycles between accesses of the MCTP send client to the memory arbiter. This value provides a bit rate of 200 Kb/s.
Ethernet Controller I210 —Flash Map 6.7.4.2 Flexible Filter Length and Control — Offset 0x01 Bits Name Default HW Mode Description 15:8 Flexible Filter Length (Bytes) 7 Reserved Reserved. 6 Reserved Reserved. 5 Reserved Reserved. 4 Last Filter 1b Last filter. 3:2 Filter Index (0) 0x0 Filter index. 1 Reserved Reserved. Apply Filter to LAN Apply Filter to the LAN. 0b = Do not apply flex filter. 1b = Apply flex filter. 0 6.7.4.3 Bits 15:0 6.7.4.4 Bits 15:0 Note: 6.7.
Flash Map—Ethernet Controller I210 6.7.6.1 Section Header — Offset 0x0 Bits Name 15:8 Block CRC8 7:0 Block Length 6.7.6.2 Default HW Mode 0x9 Description Section length in words. Rx Mode Control1 (RR_CTRL[15:0]) - Offset 0x1 Bits Name Default HW Mode Description 15:2 Reserved Reserved. Should be set to 0x0. 1 CRC Strip Enable When set, CRC field is stripped from incoming NC-SI packets. 0 NC-SI Loopback Enable When set, enables NC-SI Tx to Rx loop.
Ethernet Controller I210 —Flash Map 6.7.6.7 MAC Tx Control Reg2 (TxCntrlReg1 (31:16]) - Offset 0x6 Bits 15:0 Name Reserved 6.7.6.8 Reserved Reserved. Should be set to 0x0. Name Default HW Mode Reserved 6.7.6.9 Description Reserved Reserved. Should be set to 0x0. NC-SI Flow Control XOFF - Offset 0x8 Bits 15:0 Description Reserved - Offset 0x7 Bits 15:0 Default HW Mode Name Default HW Mode Description Reserved Tx buffer watermark for sending a XOFF NC-SI flow control packet in bytes.
Flash Map—Ethernet Controller I210 6.7.7 Traffic Type Parameters – (Global MNG Offset 0xB) 6.7.7.1 Section Header — Offset 0x0 Bits 15:8 Block CRC8 7:0 Block Length 6.7.7.2 1:0 0x1 Description Reserved Reserved Reserved Traffic Types 00b = Reserved. 01b = Network to MC traffic only allowed. 10b = OS2BMC traffic only allowed. 11b = Both Network to MC traffic and OS2BMC traffic allowed. Notes: 1.
Ethernet Controller I210 —Flash Map Table 6-8. PHY Auto Configuration Structure Format Offset High Byte[15:8] Low Byte[7:0] Section 0x0 Section length = 2*n (n – number of registers to configure) Section 6.7.8.1.1 0x1 Block CRC8. Section 6.7.8.1.2 0x2 PHY number and PHY register address. Section 6.7.8.1.3 0x3 PHY data (MDIC[15:0] or I2CCMD[15:0]). Section 6.7.8.1.4 … 2*n PHY number and PHY register address Section 6.7.8.1.3 2*n + 1 PHY data (MDIC[15:0] or I2CCMD[15:0]) Section 6.7.8.
Flash Map—Ethernet Controller I210 6.7.8.1.4 PHY Data (Offset 2*n + 1; [n = 1... Section Length]) Bits Default HW Mode Name 15:0 MDIC[15:0]/I2CCMD[15:0] value (data). See Section 8.2.4 and Section 8.17.8 for information MDIC and I2CCMD registers, respectively. Reg_Data 6.7.9 Description SVR Control Pointer – (Global MNG Offset 0x10) Bit Name 15:0 Description Pointer to SVR/LVR control configuration structure. Refer to Section 6.7.9.1 for details of the structure.
Ethernet Controller I210 —Flash Map 6.7.9.1.2 Block CRC8 (Offset 0x1) Bit Name 15:8 Reserved 7:0 CRC8 6.7.9.1.3 CRC8 is computed over the module, header excluded (for example, starting from word offset 0x2 included). SVR/LVR Control Register Address - (Offset 2*n; [n = 1... Section Length]) Name Bits 15:5 Reserved 4:0 SVR/LVR Control Register Address 6.7.9.1.4 0x0 Name Reg_Data 6.8 Default HW Mode Description Reserved SVR/LVR Control register address to which the data is written.
Flash Map—Ethernet Controller I210 Bit Description 10 Reserved. 9 Client/not a Client NIC. This bit is used by DMIX to verify the NIC is server or client. A team is required to have server NIC or LOM. 0b = Server. 1b = Client. 8:0 Reserved (set to 00b). 6.8.2 Port Identification LED Blinking (Word 0x04) Default Flash setting for this word must be 0xFFFF. Bit Description 15:12 Reserved. 11:8 Control for LED 2 0001b = Default in STATE1 + Default in STATE2.
Ethernet Controller I210 —Flash Map Current PBA numbers have exceeded the length that can be stored as hex values in these two words. For these PBA numbers the high word is a flag (0xFAFA) indicating that the PBA is stored in a separate PBA block. The low word is a pointer to a PBA block. PBA Number Word 0x08 G23456-003 FAFA Word 0x09 Pointer to PBA Block The PBA block is pointed to by word 0x09. Word Offset Description 0x0 Reserved Length in words of the PBA block (default 0x6). 0x1...
Flash Map—Ethernet Controller I210 Bit(s) Name Function Prompt Time These bits control how long the CTRL-S setup prompt message is displayed, if enabled by DIM. 00b = 2 seconds (default). 01b = 3 seconds. 10b = 5 seconds. 11b = 0 seconds. Note: CTRL-S message is not displayed if 0 seconds prompt time is selected. 7:6 PT 5 This controls the iSCSI init message (Ctrl+D menu prompt) when iSCSI is disabled.
Ethernet Controller I210 —Flash Map Bit(s) Name Function 10:8 MODE Selects the agent’s boot order setup mode. This field changes the agent’s default behavior in order to make it compatible with systems that do not completely support the BBS and PnP Expansion ROM standards. Valid values and their meanings are: 000b = Normal behavior. The agent attempts to detect BBS and PnP Expansion ROM support as it normally does. 001b = Force Legacy mode.
Flash Map—Ethernet Controller I210 6.8.6.4 Option ROM Capabilities (Word 0x33) Word 0x33 of the Flash is used to enumerate the boot technologies that have been programmed into the Flash. This is updated by Flash configuration tools and is not updated or read by IBA. Bit(s) Name Function SIG Signature. Must be set to 01b to indicate that this word has been programmed by the agent or other configuration software. 13:5 RFU Reserved. Must be 0b. 4 ISCSI iSCSI boot is present in Flash if set to 1b.
Ethernet Controller I210 —Flash Map 6.8.6.5.1.2 Bits Version and Size - 0x0001 Field Name Default Description 15:8 Size 0x06 Total size in bytes of section. 7:0 Version 0x01 Version of this structure. Should be set to 0x1. 6.8.6.5.1.3 Bits VLAN Tag - 0x0002 Field Name Default 15:13 Priority (0-7) 0x0 12 Reserved 0x0 11:0 VLAN ID (1- 4095) 0x0 Description Priority 0-7. Always 0. VLAN ID (1-4095). 6.8.7 iSCSI Boot Words 6.8.7.
Flash Map—Ethernet Controller I210 Configuration Item Offset (Bytes) Size in Bytes Comments Boot Signature 0x1:0x0 2 0x5369 (‘i’, ‘S’) Block Size 0x3:0x2 2 The structure size is stored in this field and is set depending on the amount of free Flash space available. The total size of this structure, including variable length fields, must fit within this space. 0x0384 - single port. Structure Version 0x4 1 Version of this structure. Should be set to one.
Ethernet Controller I210 —Flash Map Configuration Item Offset (Bytes) Size in Bytes Comments CHAP User Name 0x2CF:0x250 127 + 1 The user name must be non-null value and maximum size of user name allowed is 127 characters. Vlan ID 0x2D1:0x2D0 2 Vlan Id to be used for iSCSI boot traffic. a valid Vlan ID is between 1 and 4094 Mutual CHAP Password 0x2E3:0x2D2 16 + 2 The minimum mutual CHAP secret must be 12 octets and maximum CHAP secret size is 16.
Flash Map—Ethernet Controller I210 The offset is relative to the beginning of the secured firmware image. It is expressed in a 4 KB sector index, which is indicated by setting to 1b the word’s most significant bit. The offset must be programmed in such a way that the mDNS records be mapped next tom the FW image. For instance, if the FW image area is provisioned up to 448 KB, the default value is 0x8070.
Ethernet Controller I210 —Flash Map Table 6-10. Header and Body of the Firmware Secured Module (Continued) Number of Words Field or Segment Name Description and Comments Module Format Version + CRC8 Bit 15 = CRC8 field is used. Set to 1b if a CRC8 is computed over the module, set to 0b otherwise. Bits 14:8 = Module format version. Set to 0x02 is this currently defined format is used. Bits 7:0 = CRC8 value computed over the parent module only.
Flash Map—Ethernet Controller I210 6.9.2 Trailer of the Firmware Secured Module In Table 6-11, fields colored in cyan are protected by the authentication signature. The last two 4 KB sectors of the firmware secured module have the following format: Table 6-11. Trailer Format Number of Words 1 1 Field or Segment Name Flash Devices Table Version Default is 0xFFFF, which means the sector is empty and the remaining words are discarded and filled with all 1s.
Ethernet Controller I210 —Flash Map Table 6-11. Trailer Format (Continued) Number of Words Field or Segment Name Description and Comments Minimum FW Code Revision Minimum firmware code revision number required for being able to parse the RO updates section. It must be lower or equal to the Firmware Code Revision number read from the module Header listed in Table 6-10. RO Updates Length Number of RO updates words (M), starting from next word.
Flash Map—Ethernet Controller I210 6.9.2.2 Format of the RO Updates The RO Updates words can contains the following 3 structures: 1. Shadow RAM Word Write Command (2 words) 2. CSR Write Command (4 words) 3. Shadow RAM contents, from word 0x0 to 0x7F8 included The first two structures start with a Type field. Table 6-12 lists the supported values for the Type field. Table 6-12. Supported Type Fields Type Description 001b Word autoload. 010b CSR autoload. Other Invalid type, parsing is stopped here.
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Inline Functions—Ethernet Controller I210 7.0 Inline Functions 7.1 Receive Functionality Typically, packet reception consists of recognizing the presence of a packet on the wire, performing address filtering, storing the packet in the receive data FIFO, transferring the data to one of the 4 receive queues in host memory, and updating the state of a receive descriptor. A received packet goes through two stages of filtering.
Ethernet Controller I210 —Inline Functions If there is insufficient space in the receive FIFO, hardware drops the packet and indicates the missed packet in the appropriate statistics registers. When the packet is routed to a queue with the SRRCTL.Drop_En bit set to 1b, receive packets are dropped when insufficient receive descriptors exist to write the packet into system memory. Note: CRC errors before the SFD are ignored.
Inline Functions—Ethernet Controller I210 7.1.1.1 MAC Address Filtering Figure 7-2 shows the MAC address filtering. A packet passes successfully through the MAC address filtering if any of the following conditions are met: 1. It is a unicast packet and promiscuous unicast filtering is enabled. 2. It is a multicast packet and promiscuous multicast filtering is enabled. 3. It is a unicast packet and it matches one of the unicast MAC filters. 4.
Ethernet Controller I210 —Inline Functions 7.1.1.1.1 Unicast Filter The entire MAC address is checked against the 16 host unicast addresses. The 16 host unicast addresses are controlled by the host interface (the MC must not change them). The other 4 addresses are dedicated to management functions and are only accessed by the MC. The destination address of an incoming packet must exactly match one of the pre-configured host address filters. These addresses can be unicast or multicast.
Inline Functions—Ethernet Controller I210 MAC address filtering No Packet has VLAN Header Yes No Host VLAN Filters enable Yes Yes PASS L2 host VLAN Filters pass No MNG Only Check Figure 7-3. I210 VLAN Filtering 7.1.1.3 Manageability Filtering Discard packet Manageability filtering is described in Section 10.3. Figure 7-4 shows the manageability portion of the packet filtering and it is brought here to make the receive packet filtering functionality description complete.
Ethernet Controller I210 —Inline Functions Packet received from LAN Yes RCV EN No RCV All Pass decision filters No Yes No Yes Fixed Net type No Yes Yes EN XSUM Yes Match Net type No XSUM error Yes No No MNGONLY Send packet to MNG Not considered For MNG Yes Block packet from Host Figure 7-4. Manageability Filtering 7.1.1.4 Size Filtering A packet is defined as undersize if it is smaller than 64 bytes. A packet is defined as oversize in the following conditions: • The RCTL.
Inline Functions—Ethernet Controller I210 • The RCTL.LPE bit is set to 1b and the packet is bigger than RLPML.RLPML bytes. Note: Even when the RCTL.LPE bit is set, the maximum supported received-packet size is 9.5 KB (9728 bytes). 7.1.2 Receive Queues Assignment The following filter mechanisms determines the destination of a receive packet.
Ethernet Controller I210 —Inline Functions b. Queue by Flex filter (if a match) c. Queue by 2-tuple filter (if a match) 5. Queue by VLAN Priority (if a match) 6. Queue by RSS (if RSS enabled) - Identifies one of 1 x 4 queues through the RSS index. The following modes are supported: — No RSS — The default queue as defined in MRQC.DEF_Q is used for packets that do not meet any of the previous conditions. — RSS only — A set of 4 queues is allocated for RSS. The queue is identified through the RSS index.
Inline Functions—Ethernet Controller I210 Start Packet matches MAC Address Filter? Yes The MAC Address filter defines the Rx Queue Yes The L2 EtherType filter defines the Rx Queue No Packet matches L2 EtherType Filter? No RFCTL.
Ethernet Controller I210 —Inline Functions 7.1.2.2 Queue Configuration Registers Configuration registers (CSRs) that control queue operation are replicated per queue (total of 4 copies of each register). Each of the replicated registers correspond to a queue such that the queue index equals the serial number of the register (such as register 0 corresponds to queue 0, etc.).
Inline Functions—Ethernet Controller I210 Note: Software should not assign the same Ether-type value to different ETQF filters with different Rx Queue assignments. Note: The Etype Length and Etype Length Enable should only be used when parsing beyond the defined Ethertype is required to enable Rx offloading for non L2 only packets. Note: Queuing and Immediate interrupt decisions for an incoming packet that matches more than a single ETQF entry are done according to the setting of the last ETQF match.
Ethernet Controller I210 —Inline Functions In D0 mode these filters enable forwarding of packets that match up to 128 Bytes defined in the filter to one of the receive queues. In D3 mode these filters can be used for Wake-on-Lan as described in Section 5.6.3.1.8 or proxying as described in Section 5.7. Once enabled, the flexible filters scan incoming packets for a match.
Inline Functions—Ethernet Controller I210 VLAN priority filters are configured via the VLANPQF registers as follows: • Queue En — Enables forwarding of packets for each VLAN priority to a specific queue. • Rx Queue field — Contains the destination queue for each VLAN priority packet. 7.1.2.8 VLAN Tag Filters The I210 can forward packets according to their VLAN tag to separate queues. The I210 supports the configuration of the destination queue per VLAN tag.
Ethernet Controller I210 —Inline Functions 2. A hash calculation is performed. The I210 supports a single hash function, as defined by Microsoft* RSS. The I210 does not indicate to the software device driver which hash function is used. The 32bit result is fed into the packet receive descriptor. 3. The seven LSB bits of the hash result are used as an index into a 128-entry indirection table. Each entry provides a 3-bit RSS output index. When RSS is disabled, packets are assigned an RSS output index = zero.
Inline Functions—Ethernet Controller I210 7.1.2.10.1 RSS Hash Function Section 7.1.2.10.1 provides a verification suite used to validate that the hash function is computed according to Microsoft* nomenclature. The I210 hash function follows Microsoft* definition. A single hash function is defined with several variations for the following cases: • TcpIPv4 — The I210 parses the packet to identify an IPv4 packet containing a TCP segment per the criteria described later in this section.
Ethernet Controller I210 —Inline Functions 2. If UdpIPv6Ex is enabled, try using UdpIPv6Ex function; else if UpdIPv6 is enabled try using UdpIPv6 function. 3. If IPv6Ex is enabled, try using the IPv6Ex function, else if IPv6 is enabled, try using the IPv6 function. The following combinations are currently supported: • Any combination of IPv4, TcpIPv4, and UdpIPv4. • And/or. • Any combination of either IPv6, TcpIPv6, and UdpIPv6 or IPv6Ex, TcpIPv6Ex, and UdpIPv6Ex.
Inline Functions—Ethernet Controller I210 7.1.2.10.1.1 Hash for IPv4 with TCP Concatenate SourceAddress, DestinationAddress, SourcePort, DestinationPort into one single bytearray, preserving the order in which they occurred in the packet: Input[12] = @12-15, @16-19, @20-21, @22-23. Result = ComputeHash(Input, 12); 7.1.2.10.1.
Ethernet Controller I210 —Inline Functions Assume that the random key byte-stream is: 0x6d, 0x41, 0xd0, 0x77, 0x6a, 0x5a, 0x67, 0xca, 0xcb, 0x42, 0x56, 0x25, 0x2b, 0x2d, 0xb7, 0xda, 0x3d, 0xcb, 0xa3, 0x3b, 0x25, 0x43, 0xae, 0x80, 0xbe, 0x5b, 0xa3, 0x7b, 0x30, 0xac, 0x0e, 0x8f, 0x30, 0xf2, 0x01, 0xc2, 0xb0, 0xb4, 0x0c, 0xfa 7.1.2.10.3.1 IPv4 Table 7-1. IPv4 Destination Address/Port Source Address/Port IPv4 Only IPv4 With TCP 161.142.100.80:1766 66.9.149.187:2794 0x323e8fc2 0x51ccc178 65.
Inline Functions—Ethernet Controller I210 If SRRCTL[n].BSIZEPACKET is set to zero for any queue, the buffer size defined by RCTL.BSIZE is used. Otherwise, the buffer size defined by SRRCTL[n].BSIZEPACKET is used. If the receive buffer size is selected by bit settings in the Receive Control (RCTL.BSIZE) buffer sizes of 256, 512, 1024, and 2048 bytes are supported. If the receive buffer size is selected by SRRCTL[n].BSIZEPACKET, buffer sizes of 1KB to 127 KB are supported with a resolution of 1 KB.
Ethernet Controller I210 —Inline Functions Length Field (16) Length covers the data written to a receive buffer including CRC bytes (if any). Software must read multiple descriptors to determine the complete length for a packet that spans multiple receive buffers. Fragment Checksum (16) This field is used to provide the fragment checksum value. This field equals to the unadjusted 16-bit ones complement of the packet.
Inline Functions—Ethernet Controller I210 VP Field The VP field indicates whether the incoming packet's type matches the VLAN Ethernet Type programmed in the VET Register. For example, if the packet is a VLAN (802.1Q) type, it is set if the packet type matches VET and CTRL.VME is set (VLAN mode enabled). It also indicates that VLAN has been stripped from the 802.1Q packet. For more details, see Section 7.4.
Ethernet Controller I210 —Inline Functions IPE/L4E The IP and TCP/UDP checksum error bits from Table 7-7 are valid only when the IPv4 or TCP/UDP checksum(s) is performed on the received packet as indicated via IPCS and L4CS. These, along with the other error bits, are valid only when the EOP and DD bits are set in the descriptor. Note: Receive checksum errors have no effect on packet filtering. If receive checksum offloading is disabled (RXCSUM.IPOFLD and RXCSUM.TUOFLD), the IPE and L4E bits are 0b.
Inline Functions—Ethernet Controller I210 Note: The I210 does not support null descriptors (a descriptor with a packet or header address that is always equal to zero). When software sets the NSE bit in the receive descriptor, the I210 places the received packet associated with this descriptor in memory at the packet buffer address with NSE set in the PCIe attribute fields. NSE does not affect the data written to the header buffer address.
Ethernet Controller I210 —Inline Functions Table 7-11. RSS Type Packet Type Description 0x8 HASH_UDP_IPV6 0x9 HASH_UDP_IPV6_EX 0xA:0xF Reserved The I210 must identify the packet type and then choose the appropriate RSS hash function to be used on the packet. The RSS type reports the packet type that was used for the RSS hash function.
Inline Functions—Ethernet Controller I210 reflect the size of the data actually stored in the header buffer because the I210 fills the buffer up to the size configured by SRRCTL[n].BSIZEHEADER, which might be larger than the header size reported here. This field is only valid in the first descriptor of a packet and should be ignored in all subsequent descriptors. Note: When the packet is time stamped and the time stamp is placed at the beginning of the buffer the RDESC.
Ethernet Controller I210 —Inline Functions Table 7-13. Receive Status (RDESC.STATUS) Layout of the Last Descriptor 19 18 17 16 15 14 13 MC Rsv Rsv TS TSIP VEXT Rsv PIF IPCS L4I UDPCS 9 8 7 6 5 4 12 11 10 Strip CRC LLINT UDPV VP Rsv EOP DD 3 2 1 0 Reserved Table 7-14. Receive Status (RDESC.STATUS) Layout of Non-Last Descriptor ... 19 ............................ Reserved 2 1 0 EOP = 0b DD MC (19) - Packet received from MC.
Inline Functions—Ethernet Controller I210 Extended Error (12) Table 7-15 and the text that follows describes the possible errors reported by hardware. Table 7-15. Receive Errors (RDESC.ERRORS) Layout 11 10 9 RXE IPE L4E 8 7 Reserved 6 4 Reserved 3 HBO 2 0 Reserved RXE (bit 11) RXE is described in the legacy descriptor format in Section 7.1.4. IPE (bit 10) The IPE error indication is described in the legacy descriptor format in Section 7.1.4.
Ethernet Controller I210 —Inline Functions VLAN Tag (16) These bits are described in the legacy descriptor format in Section 7.1.4. 7.1.4.3 Receive Descriptor Fetching The fetching algorithm attempts to make the best use of PCIe bandwidth by fetching a cache-line (or more) descriptor with each burst. The following paragraphs briefly describe the descriptor fetch algorithm and the software control provided. When the RXDCTL[n].
Inline Functions—Ethernet Controller I210 For applications where the latency of received packets is more important than the bus efficiency and the CPU utilization, an EITR value of zero can be used. In this case, each receive descriptor are written to the host immediately. If RXDCTL[n].WTHRESH equals zero, then each descriptor are written back separately;, otherwise, write back of descriptors can be coalesced if descriptor accumulates in the internal descriptor ring due to bandwidth constrains.
Ethernet Controller I210 —Inline Functions Software inserts receive descriptors by advancing the tail pointer(s) to refer to the address of the entry just beyond the last valid descriptor. This is accomplished by writing the descriptor tail register(s) with the offset of the entry beyond the last valid descriptor. The hardware adjusts its internal tail pointer(s) accordingly. As packets arrive, they are stored in memory and the head pointer(s) is incremented by hardware.
Inline Functions—Ethernet Controller I210 latency interrupt (associated with the relevant receive queue) once the amount of free descriptors is less or equal than the threshold. The threshold is defined in 16 descriptors granularity per queue in the SRRCTL[n].RDMTS field. 7.1.5 Header Splitting and Replication 7.1.5.1 Purpose This feature consists of splitting or replicating packet's header to a different memory space.
Ethernet Controller I210 —Inline Functions 7.1.5.2 Description In Figure 7-8 and Figure 7-9, the header splitting and header replication modes are shown. 63 32 31 0 Packet Buffer Address 8 Header Buffer Address 0 Header Header Buffer 1 Payload Buffer 0 Payload Host Memory Figure 7-8.
Inline Functions—Ethernet Controller I210 The physical address of each buffer is written in the Buffer Addresses fields. The sizes of these buffers are statically defined by BSIZEPACKET and BSIZEHEADER fields in the SRRCTL[n] registers. The packet buffer address includes the address of the buffer assigned to the replicated packet, including header and data payload portions of the received packet. In the case of a split header, only the payload is included.
Ethernet Controller I210 —Inline Functions Software Notes: • If SRRCTL[n].NSE is set, all buffers' addresses in a packet descriptor must be word aligned. • Packet header can't span across buffers, therefore, the size of the header buffer must be larger than any expected header size. Otherwise, only the part of the header fitting the header buffer is replicated. In the case of header split mode (SRRCTL[n].DESCTYPE = 010b), a packet with a header larger than the header buffer is not split. • Section A.
Inline Functions—Ethernet Controller I210 7.1.7 Receive Packet Checksum and SCTP CRC Offloading The I210 supports the off loading of four receive checksum calculations: packet checksum, fragment payload checksum, the IPv4 header checksum, and the TCP/UDP checksum. In addition, SCTP CRC32 calculation is supported as described in Section 7.1.7.3 The packet checksum and the fragment payload checksum shares the same location as the RSS field and is reported in the receive descriptor when the RXCSUM.
Ethernet Controller I210 —Inline Functions Table 7-18.
Inline Functions—Ethernet Controller I210 IPv4 headers are accepted if they are any size greater than or equal to five (Dwords). If the IPv4 header is properly decoded, the IP checksum is checked for validity. The RXCSUM.IPOFLD bit must be set for this filter to pass. 7.1.7.1.4 IPv6 Filter This filter checks for valid IPpv6 headers, which are a fixed size and have no checksum. The IPv6 extension headers accepted are: hop-by-hop, destination options, and routing.
Ethernet Controller I210 —Inline Functions Table 7-20. Header Type Encoding and Lengths Header Length (Units are Bytes Unless Otherwise Specified) Header Next Header Type IPv6 6 Always 40 bytes IPv4 4 Offset Bits[7:4] Unit = 4 bytes TCP 6 Offset Byte[12].
Inline Functions—Ethernet Controller I210 Table 7-21. Descriptor Fields Incoming Packet Type Fragment Checksum (if RXCSUM.PCSD is cleared) UDPV UDPCS / L4CS /L4I Non IP Packet Packet checksum 0b 0b / 0b /0b IPv6 Packet Packet checksum 0b Depends on transport header. Non fragmented IPv4 packet Packet checksum 0b Depends on transport header. Fragmented IPv4, when not first fragment The unadjusted one’s complement checksum of the IP payload.
Ethernet Controller I210 —Inline Functions In addition, the I210 supports SCTP offloading for transmit requests. See section Section 7.2.5.3 for details about SCTP. Table 1-11 provides a high level description of all data/control transformation steps needed for sending Ethernet packets to the line. 7.2.1.1 Transmit Data Storage Data is stored in buffers pointed to by the descriptors.
Inline Functions—Ethernet Controller I210 Each advanced data descriptor that uses any of the advanced offloading features must refer to a context. Contexts can be initialized with a transmit context descriptor and then used for a series of related transmit data descriptors. The context, for example, defines the checksum and offload capabilities for a given type of TCP/IP flow. All packets of this type can be sent using this context.
Ethernet Controller I210 —Inline Functions 7.2.2.1 Legacy Transmit Descriptor Format Legacy descriptors are identified by having bit 29 of the descriptor (TDESC.DEXT) set to 0b. In this case, the descriptor format is defined as shown in Table 7-23. Note that the address and length must be supplied by software. Also note that bits in the command byte are optional, as is the CSO field. Table 7-23.
Inline Functions—Ethernet Controller I210 CSO is in a unit of bytes and must be in the range of data provided to the I210 in the descriptors. For short packets that are not padded by software, CSO must be in the range of the unpadded data length, not the eventual padded length (64 bytes). CSO must be set to the location of TCP checksum in the packet. Checksum calculation is not done if CSO is out of range. This occurs if (CSO > length - 1). In the case of an 802.
Ethernet Controller I210 —Inline Functions RS: Signals the hardware to report the status information. This is used by software that does inmemory checks of the transmit descriptors to determine which ones are done. For example, if software queues up 10 packets to transmit, it can set the RS bit in the last descriptor of the last packet.
Inline Functions—Ethernet Controller I210 • VLAN ID - the 12-bit tag indicating the VLAN group of the packet. • Canonical Form Indication (CFI) - Set to zero for Ethernet packets. • PRI - indicates the priority of the packet. Note: The VLAN tag is sent in network order (also called big endian). 7.2.2.2 Advanced Transmit Context Descriptor Table 7-29.
Ethernet Controller I210 —Inline Functions 7.2.2.2.3 LaunchTime (25) The LaunchTime field is only used in Qav mode when a queue is configured as SR queue. The LaunchTime value is used to 1. calculate the fetch time - this time defines the time to fetch the packet from the host to the packet buffer, and 2. define the launch time - the time to transmit a packet from the packet buffer. The LaunchTime is a 25 bit field defined in 32 nsec units (Launch time = LaunchTime * 32).
Inline Functions—Ethernet Controller I210 7.2.2.2.7 IDX (3) Index into the hardware context table where this context is stored. In the I210 the 2 available register context sets per queue are accessed using the LSB bit and the two MSB bits are reserved and should always be 0. Note: In Qav mode for the SR queues a valid context descriptor should be placed ahead of any timed packet pointed by a data descriptor and the IDX field is ignored. 7.2.2.2.8 L4LEN (8) Layer 4 header length.
Ethernet Controller I210 —Inline Functions 7.2.2.3 Advanced Transmit Data Descriptor Table 7-33. Advanced Transmit Data Descriptor (TDESD) Layout - (Type = 0011b) 0 Address[63:0] 8 PAYLEN 63 POPTS 46 45 40 RSV1 39 IDX 38 STA 36 35 32 DCMD 31 24 DTYP MAC RSV1 23 20 19 18 17 16 DTALEN 15 0 1. RSV - Reserved Table 7-34.
Inline Functions—Ethernet Controller I210 7.2.2.3.3 MAC (2) Table 7-35. Transmit Data (TDESD.MAC) Layout 1 0 2STEP_1588 1STEP_1588 • 1STEP_1588 (bit 1) - Sample IEEE1588 Timestamp and post it in the transmitted packet at the offset defined by the 1588_Offset field in the TSYNCTXCTL register. • 2STEP_1588 (bit 1) - Sample IEEE1588 Timestamp at packet transmission in the TXSTMP registers. Note: The two flags 1STEP_1588 and 2STEP_1588 are mutually. 7.2.2.3.
Ethernet Controller I210 —Inline Functions RS signals hardware to report the status information. This is used by software that does in-memory checks of the transmit descriptors to determine which ones are done. For example, if software queues up 10 packets to transmit, it can set the RS bit in the last descriptor of the last packet.
Inline Functions—Ethernet Controller I210 When DCMD.TSE in TDESD is set, TXSM must be set to 1b. If this bit is set, the packet should at least contain a TCP header. IXSM, when set to 1b, indicates that IP checksum must be inserted. For IPv6 packets this bit must be cleared. If the DCMD.TSE bit is set in data descriptor, and TUCMD.IPV4 is set in context descriptor, POPTS.IXSM must be set to 1b as well. If this bit is set, the packet should at least contain an IP header. 7.2.2.3.
Ethernet Controller I210 —Inline Functions Circular Buffer Base Head Transmit Queue Tail Base + Size Figure 7-10. Transmit Descriptor Ring Structure The shaded boxes in the figure represent descriptors that are not currently owned by hardware that software can modify.
Inline Functions—Ethernet Controller I210 • Tx Descriptor Completion Write–Back Address High/Low Registers (TDWBAH/TDWBAL 0-3): These registers hold a value that can be used to enable operation of head write-back operation. When TDWBAL.Head_WB_En is set and the RS bit is set in the Tx descriptor, following corresponding data upload into packet buffer, the I210 writes the Transmit Descriptor Head value for this queue to the 64 bit address specified by the TDWBAH and TDWBAL registers.
Ethernet Controller I210 —Inline Functions Note: The starvation level of a queue corresponds to the number of descriptors above the prefetch threshold (TXDCTL[n].PTHRESH) that are already in the internal queue. The queue is more starved if there are less descriptors in the internal transmit descriptor cache. Comparing starvation level might be done roughly, not at the single descriptor level of resolution.
Inline Functions—Ethernet Controller I210 For the first condition, write-backs are immediate. This is the default operation and is backward compatible with previous Intel Ethernet controllers. The other two conditions are only valid if descriptor bursting is enabled (Section 8.12.15). In the second condition, the EITR counter is used to force timely write-back of descriptors. The first packet after timer initialization starts the timer.
Ethernet Controller I210 —Inline Functions 2. The WB_on_EITR bit enables head write upon EITR expiration. When Head write back operation is enabled (TDWBAL[n].Head_WB_En = 1) setting the TDWBAL[n].WB_on_EITR bit to 1b enables placing an upper limit on delay of head write-back operation. The 30 upper bits of the TDWBAL[n] register hold the lowest 32 bits of the head write-back address, assuming that the two last bits are zero. The TDWBAH[n] register holds the high part of the 64-bit address.
Inline Functions—Ethernet Controller I210 • The protocol stack calculates the number of packets required to transmit this block based on the MTU size of the media and required packet headers. For each packet of the data block: • Ethernet, IP and TCP/UDP headers are prepared by the stack. • The stack interfaces with the software device driver and commands it to send the individual packet. • The software device driver gets the frame and interfaces with the hardware.
Ethernet Controller I210 —Inline Functions 7.2.4.2.2 TCP Segmentation Write-Back Modes Since the TCP segmentation mode uses the buffers that contains the L3/L4 header multiple times, there are some limitations on the usage of different combinations of writeback and buffer release methods in order to guarantee the header buffer’s availability until the entire packet is processed. These limitations are listed in Table 7-38. Table 7-38.
Inline Functions—Ethernet Controller I210 7.2.4.4 Packet Format Typical TCP/IP transmit window size is 8760 bytes (about 6 full size frames). Today the average size on corporate Intranets is 12-14 KB, and normally the maximum window size allowed is 64KB (unless Windows Scaling - RFC 1323 is used). A TCP message can be as large as 256 KB and is generally fragmented across multiple pages in host memory.
Ethernet Controller I210 —Inline Functions The TCP Segmentation prototype header is taken from the packet data itself. Software must identity the type of packet that is being sent (IPv4/IPv6, TCP/UDP, other), calculate appropriate checksum off loading values for the desired checksum, and calculate the length of the header which is pre-appended. The header might be up to 240 bytes in length. Once the TCP Segmentation context has been set, the next descriptor provides the initial data to transfer.
Inline Functions—Ethernet Controller I210 7.2.4.6 Transmit Checksum Offloading with TCP/UDP Segmentation The I210 supports checksum off-loading as a component of the TCP Segmentation off-load feature and as a standalone capability. Section 7.2.5 describes the interface for controlling the checksum offloading feature. This section describes the feature as it relates to TCP Segmentation.
Ethernet Controller I210 —Inline Functions Table 7-44. Conditions for Checksum Offloading TSO 7.2.4.7 Yes Yes TCP segment or UDP datagram with checksum off-load No No Non-IP packet or checksum not offloaded Yes Yes For TSO, checksum off-load must be done TCP/UDP/IP Headers Update IP/TCP or IP/UDP header is updated for each outgoing frame based on the IP/TCP header prototype which hardware DMA's from the first descriptor(s).
Inline Functions—Ethernet Controller I210 7.2.4.7.2 TCP/UDP/IP Headers for the Subsequent Frames The hardware makes the following changes to the headers for subsequent packets that are derived as part of a TCP segmentation context: Number of bytes left for transmission = PAYLEN - (N * MSS). Where N is the number of frames that have been transmitted.
Ethernet Controller I210 —Inline Functions IPv6 Header • Payload Length = last frame payload bytes + L4LEN + IPV6_HDR_extension1 TCP Header • Sequence Number update: Add previous TCP payload size to the previous sequence number value. This is equivalent to adding the MSS to the previous sequence number. • The flag values of the last frames are set by ANDing the flag word in the pseudo header with the DTXTCPFLGH.TCP_Flg_lst_seg register field. The default value of the DTXTCPFLGH.
Inline Functions—Ethernet Controller I210 Before taking advantage of the I210's enhanced checksum off-load capability, a checksum context must be initialized. For the normal transmit checksum off-load feature this is performed by providing the device with a Descriptor with TSE = 0b in the TDESD.DCMD field and setting either the TXSM or IXSM bits in the TDESD.POPTS field. Setting TSE = 0b indicates that the normal checksum context is being set, as opposed to the segmentation context.
Ethernet Controller I210 —Inline Functions 7.2.5.2 TCP/UDP Checksum Three fields in the Transmit Context Descriptor (TDESC) set the context of the TCP/UDP checksum off loading feature: • MACLEN • IPLEN • TUCMD.L4T TUCMD.L4T = 01b specifies that the packet type is TCP, and that the 16-bit TCP header checksum should be inserted at byte offset MACLEN + IPLEN +16. TUCMD.L4T = 00b indicates that the packet is UDP and that the 16-bit checksum should be inserted starting at byte offset MACLEN + IPLEN + 6.
Inline Functions—Ethernet Controller I210 Note: TSO is not supported for packet types for which IP checksum and TCP checksum can not be calculated. Table 7-45.
Ethernet Controller I210 —Inline Functions 7.2.7 Handling Time Sensitive Streams (802.1Qav) 7.2.7.1 Overview The 802.1Qav is part of the AVB specifications that include Timing and Synchronization for time specific applications (802.1AS), Stream Reservation (SR) protocol to guarantee the resources needed for Audio/Video (AV) streams (802.1Qat), Forwarding and queuing enhancements for time sensitive streams (802.1Qav). 802.
Inline Functions—Ethernet Controller I210 Queue 0 Head Tail Head Queue 2 Queue 1 Head Queue 3 Head Tail Tail Tail Read Request Fetch Arbiter Clock Packet Buffer 0 Transmit Data Buffers in host Memory Read Completion DMA Packet Buffers Packet Buffers Launch Arbiter Clock Round Robin Manageability Traffic Transmit MAC Figure 7-11. Transmit Architecture Qav Mode 7.2.7.
Ethernet Controller I210 —Inline Functions 7.2.7.5 Transmission Selection Transmission selection is the process of selecting the next packet to transmit, in the I210 Qav modes transmission selection includes three levels of arbitration - descriptor fetch, data fetch and data transmission. Descriptor fetch - the transmit descriptor fetch mechanism while in Qav modes is the same as in legacy mode, the complete description of descriptor fetch is described in Section 7.2.2.5.
Inline Functions—Ethernet Controller I210 Credits - Regulates the bandwidth allocation to user priorities, credits represent a single byte.
Ethernet Controller I210 —Inline Functions Start Yes QN = 0 No QN > 3 ? No Q[QN].QueueFrames > 0 ? QN = QN + 1 Yes SP (Best Effort) SR Q[QN].Mode = ? SP_WAIT_SR && Q[0,1].LnchTime minus MAX_TPKT_SIZE reached ? Yes (Qav) [Q[QN].LnchTime reached or (DataTranTIM =0)] && [(Q[QN].Credits >= Zero) or (DataTranARB=0)] ? No Yes No Send a Packet from Q[QN] Figure 7-12. Data Transmission Arbitration Operation for TransmitMode = Qav 7.2.7.5.
Inline Functions—Ethernet Controller I210 Else Credit = Credit + IdleSlope Note: During QavMode TIPG register value should not be modified from its default value of total 12 bytes IPG between packets. 7.2.7.5.3 Launch Time/Fetch Time Decision Launch time and Fetch time criteria is defined to be “pass” if either: • The Launch time/Fetch time match exactly the relevant portion of SYSTIML value — It is compared against SYSTIML[29:5], and provides transmission granularity of 0.
Ethernet Controller I210 —Inline Functions TQAVCTRL.TransmitMode (Transmit mode configuration: legacy, Qav) TQAVCTRL.DataFetchArb (Data fetch arbitration configuration: Round Robin, Most empty) • TXDCTL.Priority can be use to prioritize SR queues over SP queues TQAVCTRL.DataTranArb (Data Transmit arbitration configuration: Strict Priority, Credit Shaper Algorithm) TQAVCTRL.DataTrantim (Data Transmit Time Valid configuration - controls time based transmission) TQAVCTLRL.
Inline Functions—Ethernet Controller I210 7.3.1.1 MSI-X and Vectors MSI-X defines a separate optional extension to basic MSI functionality. Compared to MSI, MSI-X supports a larger maximum number of vectors, the ability for software to control aliasing when fewer vectors are allocated than requested, plus the ability for each vector to use an independent address and data value, specified by a table that resides in Memory Space.
Ethernet Controller I210 —Inline Functions • The EICR[31] bit is allocated to the other interrupt causes summarized in the ICR register. • A single interrupt vector is provided. 0 . . . Cause 0 7 IVAR[0] IVAR[1] IVAR[2] IVAR[3] Cause 7 Other causes RSV Queue Related causes EICR Reflect Causes ICR 30 31 Single Vector TCP timer Other Figure 7-13. Cause Mapping in Legacy Mode Table 7-48 lists the different interrupt causes into the IVAR registers. Table 7-48.
Inline Functions—Ethernet Controller I210 • The IVAR_MISC register maps a TCP timer and other events to 2 MSI-X vectors Figure 7-14 shows the allocation process. 0 IVAR Interrupt causes (queues) MSI-X Vector 3 IVAR_Misc MSI-X Vector Interrupt causes (Other) 0 EICR 24 RSV 31 Figure 7-14. Cause Mapping in MSI-X Mode Table 7-49 lists which interrupt cause is represented by each entry in the MSI-X Allocation registers.
Ethernet Controller I210 —Inline Functions 7.3.3 Legacy Interrupt Registers The interrupt logic consists of the registers listed in Table 7-50 and Table 7-51, plus the registers associated with MSI/MSI-X signaling. Table 7-50 lists the use of the registers in legacy mode and Table 7-50 lists the use of the registers when using the extended interrupts functionality Table 7-50. Interrupt Registers - Legacy Mode Register Acronym Function Interrupt Cause ICR Records interrupt conditions.
Inline Functions—Ethernet Controller I210 7.3.3.1.2 Advanced Mode In advanced mode, this register captures the interrupt causes not directly captured by the EICR. These are infrequent management interrupts and error conditions. Note that when EICR is used in advanced mode, the Rx /Tx related bits in ICR should be masked. ICR bits are cleared on register read. If GPIE.
Ethernet Controller I210 —Inline Functions The interrupt causes include: 1. The Receive and Transmit queues — Each queue (either Tx or Rx) can be mapped to one of the 4 interrupt causes bits (RxTxQ) available in this register according to the mapping in the IVAR registers 2. Indication for the TCP timer interrupt. 3. Legacy and other indications — When any interrupt in the Interrupt Cause register is active. Writing a 1b clears the corresponding bit in this register.
Inline Functions—Ethernet Controller I210 7.3.3.10 Extended Interrupt Auto Mask Enable Register (EIAM) Each bit set in this register enables clearing of the corresponding bit in the extended mask register following read or write-to-clear to EICR. It also enables setting of the corresponding bit in the extended mask register following a write-to-set to EICS. This mode is provided in case MSI-X is not used, and therefore auto-clear through EIAC register is not available.
Ethernet Controller I210 —Inline Functions 7.3.4.1 Auto-Clear In systems that support MSI-X, the interrupt vector allows the interrupt service routine to know the interrupt cause without reading the EICR. With interrupt moderation active, software load from spurious interrupts is minimized.
Inline Functions—Ethernet Controller I210 Note: In the I210 the interval granularity is 1 s so some of the LSB bits of the interval are used for the low latency interrupt moderation. For example, if the interval is programmed to 125d, the network controller guarantees the CPU is not interrupted by the network controller for at least 125 s from the last interrupt. In this case, the maximum observable interrupt rate from the adapter should not exceed 8000 interrupts/sec.
Ethernet Controller I210 —Inline Functions on the PCIe interface until the EITR counter assigned to that EICR bit has counted down to zero. As soon as the interrupt is issued, the EITR counter is reloaded with its initial value and the process repeats again. The interrupt flow should follow Figure 7-15. Load counter with interval Start count down No Counter = 0 ? Yes Yes No Interrupt active ? Yes Counter written to 0 Assert Interrupt Figure 7-15.
Inline Functions—Ethernet Controller I210 EICR clear Intr EICR clear Intr ITR delay Pkt Pkt Pkt EICR clear Intr ITR delay Pkt Pkt Pkt Pkt Pkt Figure 7-16. Case A: Heavy Load, Interrupts Moderated Intr EICR clear Intr EICR clear ITR delay Pkt Pkt Figure 7-17. Light load, Interrupts Immediately on Packet Receive 7.3.6 Rate Controlled Low Latency Interrupts (LLI) There are some types of network traffic for which latency is a critical issue.
Ethernet Controller I210 —Inline Functions • There are 8 flex filters. The content of each filter is described in Section 7.1.2.5. The immediate interrupt action of each filter can be enabled or disabled. If one of the filters detects an adequate packet, an immediate interrupt is issued. • When VLAN priority filtering is enabled, VLAN packets must trigger an immediate interrupt when the VLAN Priority is equal to or above the VLAN priority threshold.
Inline Functions—Ethernet Controller I210 The timeout should be programmable by the driver, and the driver should be able to disable the timer interrupt if it is not needed. 7.3.7.2 Description A stand-alone down-counter is implemented. An interrupt is issued each time the value of the counter is zero. The software is responsible for setting initial value for the timer in the TCPTIMER.Duration field. Kickstarting is done by writing a 1b to the TCPTIMER.KickStart bit.
Ethernet Controller I210 —Inline Functions 7.4.1 802.1Q VLAN Packet Format The following diagram compares an untagged 802.3 Ethernet packet with an 802.1Q VLAN tagged packet: Table 7-54. Comparing Packets 802.3 Packet #Octets DA 6 802.1Q VLAN Packet #Octets DA 6 6 SA 6 SA Type/Length 2 802.1Q Tag 4 Data 46-1500 Type/Length 2 CRC 4 Data 46-1500 CRC* 4 Note: The CRC for the 802.1Q tagged frame is re-computed, so that it covers the entire tagged frame including the 802.
Inline Functions—Ethernet Controller I210 • Legacy Transmit Descriptors:, The Tag Control Information (TCI) of the 802.1Q tag comes from the VLAN field (see Figure 7-8) of the descriptor. Refer to Table 7-26, for more information regarding hardware insertion of tags for transmits. • Advanced Transmit Descriptor: The Tag Control Information (TCI) of the 802.1Q tag comes from the VLAN Tag field (see Table 7.2.2.2.1) of the advanced context descriptor.
Ethernet Controller I210 —Inline Functions Note: The VFE bit does not affect whether the VLAN tag is stripped. It only affects whether the VLAN packet passes the receive filter. Table 7-56 lists reception actions per control bit settings. Table 7-56. Packet Reception Decision Table Is packet 802.1Q? CTRL. VME RCTL. VFE Action No X1 X1 Normal packet reception Yes 0b 0b Receive a VLAN packet if it passes the standard MAC address filters (only). Leave the packet as received in the data buffer.
Inline Functions—Ethernet Controller I210 • 7.4.5.2 If the regular VLAN is inserted using the switch based VLAN insertion mechanism or from the descriptor (see Section 7.4.3.1), and the packet does not contain an external VLAN, the packet is dropped, and if configured, the queue from which the packet was sent is disabled.
Ethernet Controller I210 —Inline Functions The BLINK bits control whether the LED should be blinked (on for 200ms, then off for 200ms) while the LED source is asserted. The blink control might be especially useful for ensuring that certain events, such as ACTIVITY indication, cause LED transitions, which are sufficiently visible by a human eye. Note: When LED Blink mode is enabled the appropriate LED Invert bit should be set to 0b.
Inline Functions—Ethernet Controller I210 The I210 reports parity errors in the PEIND register according to the region in which the parity error occurred (PCIe, DMA, LAN Port or Management). An interrupt is issued via the ICR.FER bit on occurrence of a parity error. Parity error interrupt generation per region can be masked via the PEINDM register.
Ethernet Controller I210 —Inline Functions 5. Re-initialize the port. 7.6.1.2 Recovery from DMA Parity Error Event To recover from a parity error condition in the DMA region, the software device driver should issue a software reset by asserting the CTRL.RST bit as specified in Section 4.3.1 and re-initializing the port. 7.6.1.
Inline Functions—Ethernet Controller I210 As shown in Figure 7-18, DCA provides a mechanism where the posted write data from an I/O device, such as an Ethernet NIC, can be placed into CPU cache with a hardware pre-fetch. This mechanism is initialized upon a power good reset. A software device driver for the I/O device configures the I/O device for DCA and sets up the appropriate DCA target ID for the device to send data.
Ethernet Controller I210 —Inline Functions Figure 7-19 shows the format of the PCIe message for DCA. +0 6 R 5 Fmt= 11 4 3 +1 2 1 Type=00000b 0 7 6 R 5 TC 4 3 +2 2 1 0 Rsv 7 6 T D E P Requester ID 5 4 Attr +3 3 2 1 0 7 6 R 5 4 3 2 1 0 Length DCA preferences Last DW BE First DW BE Address [63:32] Address [32:2] R Length specific data Length specific data TLP digest Figure 7-19. PCIe Message Format for DCA The DCA preferences field has the following formats.
Inline Functions—Ethernet Controller I210 On the PCIe link existence of a TLP Process Hint (TPH) is indicated by setting the TH bit in the TLP header. Using the PCIe TLP Steering Tag (ST) and Processing Hints (PH) fields, the I210 can provide hints to the root complex about the destination (socket ID) and about data access patterns (locality in Cache), when executing DMA memory writes or read operations.
Ethernet Controller I210 —Inline Functions 7.8 Time SYNC (IEEE1588 and IEEE 802.1AS) 7.8.1 Overview IEEE 1588 addresses the clock synchronization requirements of measurement and control systems. The protocol supports system-wide synchronization accuracy in the sub-microsecond range with minimal network and local clock computing resources. The protocol is spatially localized and allows simple systems to be installed and operate. The IEEE802.
Inline Functions—Ethernet Controller I210 transmission time at the master and its reception time at the slave. The slave calculates the time gap between consecutive SYNC packets defined by the master clock. It then calibrates itself to get the same time gap defined by its own clock. During this phase the slave also sets its time to be as close as possible to the master time (as accurate as the transmission delay and software latencies).
Ethernet Controller I210 —Inline Functions • The slave software responds back by sending the Delay_Req packet (for those SYNC packets that the slave “wish” to respond). The Delay_Req packet is indicated to the hardware by setting the 2STEP_1588 flag in the Advanced Transmit Data Descriptor. The transmission time is extracted from the TXSTMP register the same as the master processes the transmitted SYNC packets.
Inline Functions—Ethernet Controller I210 7.8.2.3 TimeSync Indications in Receive and Transmit Packet Descriptors Certain indications are transferred between software and hardware regarding PTP packets. These indications are enabled when the Disable systime bit in the TSAUXC register is cleared. Further more, transmit timestamping is enabled by the TSYNCTXCTL.EN flag. Received packets for captured time are identified according to the TSYNCRXCTL.Type and CTRLT and MSGT fields in the TSYNCRXCFG register.
Ethernet Controller I210 —Inline Functions Table 7-62. Packet Timestamp Sampling Latency at 100 Mb/s (Stand-alone Setup) Parameter Min/Max Latency Comment Tx timestamp to start of SFD on MDI 984/1024 ns Min/max values represent a possible variance over reset or link up/down events. The latency is measured with minimal PHY FIFO depth by setting bits 15:14 in the PHY TX FIFO register (MAC Specific Control Register 1 - Page 2, Register 16).
Inline Functions—Ethernet Controller I210 • Run Time - During run time the SYSTIM timer value in the SYSTIMH, SYSTIML and SYSTIMR registers, is updated periodically each 8 nS clock cycle according to the following formula: — Define: INC_TIME = 8 nsec +/- TIMINCA.Incvalue * 2-32 nsec. Add or subtract the TIMINCA.Incvalue is defined by TIMINCA.
Ethernet Controller I210 —Inline Functions — Tdelay is the transmission delay from the slave to the master. It can be calculated using T1...T4 as follow: Tdelay = [(T2-T1) + (T4-T3)] / 2 — The factor is a parameter that affects the speed of convergence. For a clock frequency of 125 MHz, an optimized factor equals 8. Table 7-65 lists the expected convergence time for some cases while Tcycle equals 1 second and the slave-to-master clock frequency difference equals 100 ppm. 7.8.3.
Inline Functions—Ethernet Controller I210 6. When the SYSTIML/H registers becomes equal or larger than the TRGTTIML/H registers that define the beginning of the pulse, the selected SDP changes its level. Then, when the SYSTIML/H registers becomes equal or larger than the other TRGTTIML/H registers (that define the trailing edge of the pulse), the selected SDP changes its level back. 7.8.3.3.
Ethernet Controller I210 —Inline Functions 2. The selected AUTT0 or AUTT1 flags are set in the TSICR register. If the AUTT interrupt is enabled by the TSIM register and the 1588 interrupts are enabled by the Time_Sync flag in the ICR register then an interrupt is asserted as well. After the hardware reports that an event time was latched, the software should read the latched time in the selected AUXSTMP registers. Software should read first the Low register and only then the High register.
Inline Functions—Ethernet Controller I210 Table 7-66.
Ethernet Controller I210 —Inline Functions Table 7-68. Message Decoding for V1 (Control Field at Offset 32) Enumeration Value PTP_SYNC_MESSAGE 0 PTP_DELAY_REQ_MESSAGE 1 PTP_FOLLOWUP_MESSAGE 2 PTP_DELAY_RESP_MESSAGE 3 PTP_MANAGEMENT_MESSAGE 4 reserved 5–255 Table 7-69.
Inline Functions—Ethernet Controller I210 Table 7-70. Enabling Receive Timestamp Functionality Register Field Setting Options TSYNCRXCTL Type Type equals to 001b enables V1 packets with Control field equals to CTRLT parameter Type equals to 010b enables V2 packets with MessageType fields equals to MSGT parameter as well as DELAY_REQ and DELAY_RESP packets.
Ethernet Controller I210 —Inline Functions Table 7-72. IEEE 802.3 Recommended Package Statistics Recommended package capability OctetsTransmittedOK I210 Counter GOTCH/GOTCL Notes and Limitations The I210 counts also the DA/SA/LT/CRC as part of the octets. The I210 doesn’t count Flow control packets. FramesWithDeferredXmissions DC LateCollisions LATECOL FramesAbortedDueToXSColls ECOL FramesLostDueToIntMACXmitError HTDMPC The I210 counts the excessive collisions in this counter, while 802.
Inline Functions—Ethernet Controller I210 Table 7-74.
Ethernet Controller I210 —Inline Functions Table 7-75. RMON Statistics (Continued) RMON statistic I210 Counters Notes etherStatsPkts256to511Octets PRC511 RMON counts bad packets as well etherStatsPkts512to1023Octets PRC1023 RMON counts bad packets as well etherStatsPkts1024to1518Octets PRC1522 RMON counts bad packets as well 7.9.4 Linux net_device_stats The I210 supports part of the net_device_stats as defined by Linux Kernel version 2.6 (defined in ).
Inline Functions—Ethernet Controller I210 7.9.5 Statistics Hierarchy The following diagram shows the relations between the packet flow and the different statistic counters.
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Programming Interface — Ethernet Controller I210 8.0 Programming Interface 8.1 Introduction This section details the programmer visible state inside the I210. In some cases, it describes hardware structures invisible to software in order to clarify a concept. The I210's address space is mapped into four regions with PCI Base Address registers described in Section 9.3.11. These regions are listed in Table 8-1. Table 8-1.
Ethernet Controller I210 — Programming Interface 8.1.1.3 Memory-Mapped Access to MSI-X Tables The MSI-X tables can be accessed as direct memory-mapped offsets from the base address register (BAR3; refer to Section 9.3.11). Refer to Section 8.1.3 for the appropriate offset for each specific internal MSI-X register. 8.1.1.4 Memory-Mapped Access to Expansion ROM The Expansion/Option ROM module located in the external Flash (refer to Section 3.3.9.1) can be accessed as a memory-mapped Expansion ROM.
Programming Interface — Ethernet Controller I210 8.1.1.5.2 IODATA (I/O Offset 0x04) The IODATA register must always be written as a Dword access when the IOADDR register contains a value for the internal register and memories (for example, 0x00000-0x1FFFC). In this case, writes that are less than 32 bits are ignored. Reads to IODATA of any size returns a Dword of data. However, the chipset or CPU might only return a subset of that Dword.
Ethernet Controller I210 — Programming Interface b. Bits 30:0 of IOADDR should hold the actual address of the internal register or memory being written to. 2. Data to be written is written into the IODATA register. — The IODATA register is used as a window to the register or memory address specified by IOADDR register. As a result, the data written to the IODATA register is written into the CSR pointed to by bits 30:0 of the IOADDR register. 3. IOADDR.
Programming Interface — Ethernet Controller I210 Reserved and/or undefined addresses: any register address not explicitly declared in this specification should be considered to be reserved, and should not be written to. Writing to reserved or undefined register addresses might cause indeterminate behavior. Reads from reserved or undefined configuration register addresses might return indeterminate values unless read values are explicitly stated for specific addresses.
Ethernet Controller I210 — Programming Interface Table 8-4. I210 Register Field Attributes (Continued) Attribute Description RC/W1C Read-only status, Write-1-to-clear status register: Read-to-clear status register. Register bits indicate status when read, a set bit indicating a status event can be cleared by writing a 1b or by reading the register. Writing a 0b to RC/ W1C bit has no effect. RS Read Set ‚Äì This is the attribute used for Semaphore bits.
Programming Interface — Ethernet Controller I210 The following exceptions use network ordering (also called big Endian). Using the previous example, a 16-bit field (EtherType) is stored in a CSR in the following manner: (DW aligned) or (Word aligned) Byte 3 Byte 2 Byte 1 Byte0 ... ... 0x00 0x01 0x00 0x01 ... ... The following exceptions use network ordering: All ETherType fields.
Ethernet Controller I210 — Programming Interface Table 8-6.
Programming Interface — Ethernet Controller I210 Table 8-6.
Ethernet Controller I210 — Programming Interface Table 8-6.
Programming Interface — Ethernet Controller I210 Table 8-6.
Ethernet Controller I210 — Programming Interface Table 8-6.
Programming Interface — Ethernet Controller I210 Table 8-6.
Ethernet Controller I210 — Programming Interface Table 8-6.
Programming Interface — Ethernet Controller I210 Table 8-6.
Ethernet Controller I210 — Programming Interface Table 8-6. Register Summary (Continued) Offset Alias Offset Abbreviation Name RW 0x01A0 N/A LTRC Latency Tolerance Reporting (LTR) Control RW 0x0E30 N/A EEER Energy Efficient Ethernet (EEE) Register RW Diagnostic 0x5BB8 N/A PCIEMISC PCIe Misc.
Programming Interface — Ethernet Controller I210 8.1.3.1 Alias Addresses Certain registers maintain an alias address designed for backward compatibility with software written for previous GbE controllers. For these registers, the alias address is listed Table 8-6. Those registers can be accessed by software at either the new offset or the alias offset. It is recommended that software that is written solely for the I210, use the new address offset. 8.1.4 MSI-X BAR Register Summary Table 8-7.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description Set Link Up Set Link Up must be set to 1b to permit the MAC to recognize the LINK signal from the PHY, which indicates the PHY has gotten the link up, and is ready to receive and transmit data. See Section 3.7.4 for more information about auto-negotiation and link configuration in the various modes. SLU ILOS 6 7 0b1 Notes: 1. The CTRL.SLU bit is normally initialized to 0b.
Programming Interface — Ethernet Controller I210 Field SDP0 DATA (RWM) Bit(s) 18 Initial Value 0b1 Description SDP0 Data Value Used to read or write the value of software-controlled I/O pin SDP0. If SDP0 is configured as an output (SDP0_IODIR = 1b), this bit controls the value driven on the pin (initial value Flash-configurable). If SDP0 is configured as an input, reads return the current value of the pin. When the SDP0_WDE bit is set, this field indicates the polarity of the watchdog indication.
Ethernet Controller I210 — Programming Interface Field DEV_RST (SC) Bit(s) 29 Initial Value Description Device Reset This bit performs a reset of the entire controller device, resulting in a state nearly approximating the state following a power-up reset or internal PCIe reset, except for system PCI configuration. 0b = Normal. 1b = Reset. This bit is self clearing. 0b Notes: 1. Asserting DEV_RST generates an interrupt via the ICR.DRSTA interrupt bit. 2. Device Reset (CTRL.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description Reserved 5 X Reserved. Write 0b, ignore on read. X Link Speed Setting Reflects the speed setting of the MAC and/or link when it is operating in 10/ 100/1000BASE-T mode (internal PHY).
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description Reserved 0 0b Reserved. Write 0b, ignore on read. I2C over SDP Enabled 1 0b1 Enable I2C over SDP0 and SDP2 pins. When set, SDP0 and SDP2 pins functions as an I2C interface operated through the I2CCMD,I2CPARAMS register set. SDP2_GPIEN 2 0b General Purpose Interrupt Detection Enable for SDP2.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description RO_DIS 17 0b Relaxed Ordering Disabled When set to 1b, the I210 does not request any relaxed ordering transactions on the PCIe interface regardless of the state of bit 4 in the PCIe Device Control register. When this bit is cleared and bit 4 of the PCIe Device Control register is set, the I210 requests relaxed ordering transactions as specified by registers RXCTL and TXCTL (per queue and per flow).
Ethernet Controller I210 — Programming Interface The bit mappings are listed in Table 8-8 for clarity. Table 8-8.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description MDI_IE 29 0b Interrupt Enable When set to 1b an Interrupt is generated at the end of an MDI cycle to indicate an end of a read or write operation to the PHY. MDI_ERR (RWM) 30 0b Error This bit is set to 1b by hardware when it fails to complete an MDI read. Software should make sure this bit is clear (0b) before issuing an MDI read or write command. Note: Reserved 31 8.2.
Ethernet Controller I210 — Programming Interface 8.2.6 Copper/Fiber Switch Control - CONNSW (0x0034; R/W) Field Bit(s) Reserved 1:0 ENRGSRC 2 Initial Value 00b 0b1 Description Reserved SerDes Energy Detect Source 0b = SerDes Energy detect source is internal. 1b = SerDes Energy detect source is from SRDS_[n]_SIG_DET pin. This bit defines the source of the signal detect indication used to set link up while in SerDes mode.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description LED0_MODE 3:0 0110b1 LED0/LINK# Mode This field specifies the control source for the LED0 output. An initial value of 0110b selects the LINK100# indication. LED_PCI_MODE 4 0b 0b = Use LEDs as defined in the other fields of this register. 1b = Use LEDs to indicate PCI3 lanes idle status in SDP mode (only when the led_mode is set to 0x8 – SDP mode) LED0 indicates electrical idle status.
Ethernet Controller I210 — Programming Interface Field Reserved Bit(s) 27:24 Initial Value Description 0000b Reserved. Reserved 29:28 0x0 Reserved. Write 0x0, ignore on read. Reserved 31:30 00b Reserved. 1. These bits are read from the Flash. 8.3 Internal Packet Buffer Size Registers The following registers define the size of the on-chip receive and transmit buffers used to receive and transmit packets. Refer to Section 4.6.
Programming Interface — Ethernet Controller I210 Bit banging access to the flash via the FLA register is not protected by this field. Field Bit(s) Reserved 5:0 Init. Description 0x0 Reserved. Reads as 0b. FLASH_IN_USE (RO) 6 0b Valid when ee_pres = 1b. When this bit is set to 1b, it indicates that the Flash is present with a valid signature and the hardware was programmed from the Flash. The hardware will always first check the existence of the external Flash. 0b = Flash is not used.
Ethernet Controller I210 — Programming Interface Field Bit(s) Reserved 31:28 Init. 0x0 Description Reserved. Reads as 0b. This register provides software direct access to the EEPROM. Software can control the EEPROM by successive writes to this register. Data and address information is clocked into the EEPROM by software toggling the EE_SK and EE_DI bits (0 and 2) of this register with EE_CS set to 0b. Data output from the EEPROM is latched into the EE_DO bit (bit 3) via the internal 62.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description EEPROM Size This field defines the size of the EEPROM: Field Value 14:112 EE_SIZE (RO) EEPROM Size EEPROM Address Size 0111b 0111b 1000b 16 Kbytes 32 Kbytes 2 bytes 2 bytes Note: EE_BLOCKED (RO) 15 0b EEPROM access blocked EEPROM Bit Banging access blocked - Bit is set by HW when detecting an EEPROM access violation during bit banging access using the EEC register or detecting an EEPROM access violation w
Ethernet Controller I210 — Programming Interface When this register is used to read a word from the EEPROM, that word does not influence any of the I210's internal registers even if it is normally part of the auto-read sequence. Note: Register reset on LAN_PWR_GOOD only. Field Bit(s) CMDV (RO) 0 Init. Description 0b Command Valid Bit. This bit is cleared by hardware in case the read request was rejected. DONE (RO field) 1 1b Read Done. Set this bit to 1b when the EEPROM-mode read completes.
Programming Interface — Ethernet Controller I210 8.4.5 EEPROM Load Control Register - EELOADCTL (0x12020; RW) This register is used by software to control I211 auto-read operation and to execute EEPROM auto-read sequences mimicking occurrence of various resets. Note: Register reset by LAN_PWR_GOOD only. 8.4.
Ethernet Controller I210 — Programming Interface Field Bit(s) Init. Description FL_SO (RO) 3 0b Data Output Bit From Flash. The FL_SO input signal is mapped directly to this bit in the register and contains the Flash serial data output. This bit is read-only from a software perspective. Note that writes to this bit have no effect. RO bit. FL_REQ 4 0b2 Request Flash Access. Software must write a 1b to this bit to get direct Flash access. It has access when FL_GNT is set to 1b.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value FL_SCK 0 0b Clock Input to the Flash When FL_GNT is 1b, the FL_SCK out signal is mapped to this bit and provides the serial clock input to the Flash device. Software clocks the Flash memory via toggling this bit with successive writes. FL_CE 1 1b Chip Select Input to the Flash When FL_GNT is 1b, the FL_CE output signal is mapped to the chip select of the Flash device.
Ethernet Controller I210 — Programming Interface Note: The default values fit to Atmel* Serial Flash Memory devices. Notes: 1. Register reset on LAN_PWR_GOOD only. 2. Register shared by all functions. Field Bit(s) Initial Value Description DERASE 7:0 0x0062 Flash Device Erase Instruction The op-code for the Flash erase instruction. SERASE 15:8 0x0052 Flash Block Erase Instruction The op-code for the Flash block erase instruction. Relevant only to Flash access by manageability.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description ADDR 12:4 0x0 Write Address This field specifies the address offset of the EEPROM word from the start of the EEPROM Section. Sections supported are: • Common and LAN0 • LAN1 • LAN2 • LAN3 VALID_CORE2 13 0b Valid Write Active to Core 2 Write strobe to Core 2. Firmware/software sets this bit for write access to registers loaded from EEPROM words in LAN2 section.
Ethernet Controller I210 — Programming Interface Field CFG_DONE 01 CFG_DONE 11 CFG_DONE 21 Bit(s) 18 19 20 Initial Value Description 0b Configuration cycle is done for port 0 – This bit indicates that configuration cycle (configuration of SerDes, PHY, PCIe and PLLs) is done for port 0. This bit is set to 1b to indicate configuration done, and cleared by hardware on any of the reset sources that causes initialization of the PHY.
Programming Interface — Ethernet Controller I210 8.4.13.1 Management Flash Control Register - FLMNGCTL (0x12038; RW) 8.4.13.2 Management Flash Read Data - FLMNGDATA (0x1203C; RW) 8.4.13.3 Management Flash Read Counter - FLMNGCNT (0x12040; RW) 8.4.14 Flash Security - FL_SECU (0x12114; RO to host, RW to FW) 8.4.15 VPD Diagnostic Register - VPDDIAG (0x5B3C; RO to Host, RW to FW) 8.4.16 Shadow RAM Information Register - SHADOWINF (0x012068; RO) 8.4.
Ethernet Controller I210 — Programming Interface 8.4.20 Manageability Flash Read/Write Data – FLMNGDATA (0x1203C; RO to host, RW to FW) See register Software FLASH Burst Data Register - FLSWDATA in Section 8.4.37. 8.4.21 Manageability Flash Burst Access Counter – FLMNGCNT (0x12040; RO to host, RW to FW) See register Software FLASH Burst Access Counter - FLSWCNT in Section 8.4.38. 8.4.
Programming Interface — Ethernet Controller I210 Field NUM_OF_DUMMY Bit(s) 2:1 Init. Description 01b Indicates the number of dummy bytes that should be provided to the Flash after providing the address. Indicates the frequency of the clock provided to the Flash. 00b = Clock is 15.125 MHz 01b = Clock is 31.25 MHz. 10b = Clock is 62.5 MHz. 11b = Reserved.
Ethernet Controller I210 — Programming Interface 8.4.28 FLASH Read Status Register – FLASHRDST (0x12008; RW) This register holds the last read status from Flash. This register is reset only at power on or during LAN_PWR_GOOD assertion. 8.4.29 Flash Block Base Address – FLBLKBASE (0x12100; RO) Field Bit(s) Start Address 11:0 Reserved 30:12 8.4.30 0x000 Description The base address expressed in a 4 KB sector index of the Flash section, which is protected from software writes.
Programming Interface — Ethernet Controller I210 8.4.34 EEPROM Block Base Address – EEBLKBASE (0x1210C; RO) Field Bit(s) Init. Description 0x000 The base address expressed in words of the first hardware section (EEPROM map), which is protected from software writes. Loaded from the secured section in the Flash (word 0x2D). 11 Reserved. 2nd Start Address 22:12 0x000 The base address expressed in words of the second hardware section (EEPROM map), which is protected from software writes.
Ethernet Controller I210 — Programming Interface CMD{27:24} FLSWCNT.CNT range Limitations to Host Command Description 0000b 1 B - 4 KB 0001b 1 B - 256 B the write must not cross a page (256 B) boundary When in the Flash Secure mode, this command is operational only if applied on un-secured words. Write 0010b Don’t Care When in Flash secure mode, this command is operational only if applied on un-secured sectors. Flash sector (4 KB) erase (when no security).
Programming Interface — Ethernet Controller I210 8.4.39 Data - INVM_DATA (0x12120 + 4*n [n = 0..63]; R/W1) These registers holds the iNVM memory content. The iNVM memory is organized in 32 lines of 64-bits each. INVM_DATA[0] holds the lowest 32 bits of the first iNVM line. INVM_DATA[1] holds the highest 32 bits of the first iNVM line. Field Bit(s) DATA 31:0 8.4.40 Init. 0x0 Description Data value programmed or to be programmed in the corresponding iNVM line segment (high or low order 32-bits).
Ethernet Controller I210 — Programming Interface 8.5 Flow Control Register Descriptions 8.5.1 Flow Control Address Low - FCAL (0x0028; RO) Flow control packets are defined by 802.3X to be either a unique multicast address or the station address with the EtherType field indicating PAUSE. The FCA registers provide the value hardware uses to compare incoming packets against, to determine that it should PAUSE its output.
Programming Interface — Ethernet Controller I210 8.5.4 Flow Control Transmit Timer Value - FCTTV (0x0170; R/W) The 16-bit value in the TTV field is inserted into a transmitted frame (either XOFF frames or any PAUSE frame value in any software transmitted packets). It counts in units of slot time of 64 bytes. If software needs to send an XON frame, it must set TTV to 0x0 prior to initiating the PAUSE frame. Field TTV Bit(s) Initial Value 15:0 Reserved 8.5.
Ethernet Controller I210 — Programming Interface Field Reserved Bit(s) 3:0 Initial Value 17:4 0x0 Reserved 31:18 0x0 8.5.7 Reserved. Write 0x0, ignore on read. 0x0 RTH Description Receive Threshold High. FIFO high water mark for flow control transmission when transmit flow control is enabled (CTRL.TFCE = 1b). An XOFF packet is sent if the occupied space in the packet buffer is bigger or equal than this watermark. This field is in 16 bytes granularity. Refer to Section 3.7.5.3.
Programming Interface — Ethernet Controller I210 8.6 PCIe Register Descriptions 8.6.1 PCIe Control - GCR (0x5B00; RW) Field Bit(s) Initial Value Description Reserved 1:0 0x0 Reserved. Discard on BME deassertion 2 1b When set and BME deasserted, PCIe discards all requests of this function. Reserved 8:3 0x0 Reserved. Write 0x0, ignore on read. When set, enables a resend request after the completion timeout expires. 0b = Do not resend request after completion timeout.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description GIO_64_BIT_EN 28 0b Enable two 64-bit counters instead of four 32-bit counters. GIO_COUNT_RESET 29 0b Reset indication of PCIe statistical counters. GIO_COUNT_STOP 30 0b Stop indication of PCIe statistical counters. GIO_COUNT_START 31 0b Start indication of PCIe statistical counters. 8.6.
Programming Interface — Ethernet Controller I210 Table 8-9. PCIe Statistic Events Encoding Transaction Layer Events Event Mapping (Hex) Description Bad TLP From LL 0x0 For each cycle, the counter increases by one, if a bad TLP is received (bad CRC, error reported by AL, misplaced special char, or reset in thI of received tlp). Requests That Reached Timeout 0x10 Number of requests that reached time out.
Ethernet Controller I210 — Programming Interface 8.6.5 PCIe Counter #0 - GSCN_0 (0x5B20; RC) Field EVC Bit(s) 31:0 8.6.6 Bit(s) 31:0 8.6.7 EVC Bit(s) 8.6.9 Note: Description Event Counter. Type of event counted is defined by the GSCL_2.GIO_EVENT_NUM_1 field. Count value does not wrap around and remains stuck at the maximum value of 0xFF...F. Value is cleared by read. Initial Value 0x0 Description Event Counter. Type of event counted is defined by the GSCL_2.GIO_EVENT_NUM_2 field.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description Power state indication of Function. 00b = DR. 01b = D0u. 10b = D0a. 11b = D3. This field resets only by LAN_PWR_GOOD. Func Power State 1:0 00b Reserved 2 0b Reserved. Func Aux_En 3 0b Function Auxiliary (AUX) Power PM Enable bit shadow from the configuration space. Reserved 28:4 0x0 Reserved. Write 0x0, ignore on read. MNGCG 29 0b MNG Clock Gated.
Ethernet Controller I210 — Programming Interface 8.6.12 PCIe BAR Control - BARCTRL (0x5BFC; R/W) Target Field Bit(s) Reserved 31:0 Initial Value Description Reserved Write 0x0, ignore on read. 0x0 Table 8-10.
Programming Interface — Ethernet Controller I210 Bit(s) Initial Value Disable ACL 0 0b When set, the ACL check on the PCIe VDMs is disabled. Reserved 31:1 0x0 Reserved Write 0x0, ignore on read Field 8.7 Description Semaphore Registers This section contains registers used to coordinate between firmware and software. The usage of these registers is described in Section 4.6.11. 8.7.
Ethernet Controller I210 — Programming Interface 8.7.2 Firmware Semaphore - FWSM (0x5B54; RO to Host, RW to FW) Field1 EEP_FW_Semaphore Initial Value Bit(s) 0 0b Description Software/Firmware Semaphore. Firmware should set this bit to 1b before accessing the SW_FW_SYNC register. If software is using the SWSM register and does not lock SW_FW_SYNC, firmware is able to set this bit to 1b. Firmware should set this bit back to 0b after modifying the SW_FW_SYNC register.
Programming Interface — Ethernet Controller I210 Field1 Ext_Err_Ind Initial Value Bit(s) 24:19 0x0 Description External Error Indication Firmware writes here the reason that the firmware operation has stopped. For example, Flash CRC error, etc. Possible values: 0x00: No Error. 0x01: Flash CRC error in test configuration module. Reserved. 0x03: Flash CRC error in common firmware parameters module. 0x04: Flash CRC error in pass through. 0x05: Shadow RAM dump fault. 0x06: Bad Flash contents.
Ethernet Controller I210 — Programming Interface 8.7.3 Software–Firmware Synchronization - SW_FW_SYNC (0x5B5C; RWM) This register is intended to synchronize between software and firmware. Note: If software takes ownership of bits in the SW_FW_SYNC register for a duration longer than 1 second, firmware can take ownership of the bit. Field Initial Value Bit(s) Description SW_FLASH_SM 0 0b When set to 1b, Flash access is owned by software.
Programming Interface — Ethernet Controller I210 8.8 Interrupt Register Descriptions 8.8.1 PCIe Interrupt Cause - PICAUSE (0x5B88; RW1/C) Field CA Bit(s) 0 UA 1 Init. Description 0b PCI Completion Abort Exception Issued. 0b Reserved. Write 0x0, ignore on read. BE 2 0b Wrong byte-enable exception in the FUNC unit. TO 3 0b PCI timeout exception in the FUNC unit. BMEF 4 0b Asserted when Bus-Master-Enable (BME) of the PF is de-asserted. 0b PCI Completer Abort Received.
Ethernet Controller I210 — Programming Interface Auto clear can be enabled for any or all of the bits in this register. Table 8-11. EICR Register - Non-MSI-X Mode (GPIE.Multiple_MSIX = 0b) Field Bit(s) Initial Value Description RxTxQ 3:0 0x0 Receive/Transmit Queue Interrupts.
Programming Interface — Ethernet Controller I210 Table 8-14. EICS Register - MSI-X Mode (GPIE.Multiple_MSIX = 1b) Field Bit(s) MSI-X 4:0 Reserved 31:5 8.8.5 Initial Value Description 0x0 Sets the corresponding EICR bit of MSI-X vectors 4:0 0x0 Reserved. Write 0x0, ignore on read. Extended Interrupt Mask Set/Read - EIMS (0x1524; RWM) Reading this register returns which bits that have an interrupt mask set.
Ethernet Controller I210 — Programming Interface Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing a 1b to the corresponding bit location (as defined in the EICR register) of that interrupt in this register. Bits written with 0b are unchanged (their mask status does not change). Table 8-17. EIMC Register - Non-MSI-X Mode (GPIE.
Programming Interface — Ethernet Controller I210 In MSI-X mode, this register controls which of the bits in the EIMS register to clear upon interrupt generation if enabled via the GPIE.EIAME bit. Note: When operating in MSI mode and setting any bit in the EIAM register causes the clearing of all bits in the EIMS register and the masking of all interrupts after generating a MSI interrupt. Table 8-20. Field EIAM Register - Non-MSI-X Mode (GPIE.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description RXDMT0 4 0b Receive Descriptor Minimum Threshold Reached. Indicates that the minimum number of receive descriptors are available and software should load more receive descriptors. Reserved 5 0b Reserved. Write 0x0, ignore on read. Rx Miss 6 0b Missed packet interrupt is activated for each received packet that overflows the Rx packet buffer (overrun).
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description SCE 25 0b DMA Coalescing Clock Control Event. This bit is set when the multicast or broadcast DMA coalescing clock control mechanism is activated or de-activated. Software WD 26 0b Software Watchdog. This bit is set after a software watchdog timer times out. Reserved 27 0b Reserved. Write 0x0, ignore on read. Reserved 28 0b Reserved. TCP Timer 29 0b TCP Timer Interrupt.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description Reserved. Write 0x0, ignore on read. Reserved 21:20 0x0 FER 22 0b Sets the Fatal Error interrupt. 0b Reserved. Write 0b, ignore on read. Reserved 23 PCI Exception 24 0b Sets the PCI Exception interrupt. SCE 25 0b Sets the DMA Coalescing Clock Control Event interrupt. Software WD 26 0b Sets the Software Watchdog interrupt. Reserved 27 0b Reserved. Write 0b, ignore on read.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description GPI_SDP1 12 0b Sets/Reads the mask for General Purpose Interrupt, related to SDP1 pin. GPI_SDP2 13 0b Sets/Reads the mask for General Purpose Interrupt, related to SDP2 pin. GPI_SDP3 14 0b Sets/Reads the mask for General Purpose Interrupt, related to SDP3 pin. Reserved 17:15 0x0 Reserved. Write 0x0, ignore on read. MNG 18 0b Sets/reads the mask for Management Event interrupt.
Ethernet Controller I210 — Programming Interface Field Bit(s) RXDMT0 4 Reserved 5 Initial Value Description 0b Clears the mask for Receive Descriptor Minimum Threshold Hit interrupt. 0b Reserved. Write 0b, ignore on read. Rx Miss 6 0b Clears the mask for the Rx Miss interrupt. RXDW 7 0b Clears the mask for the Receiver Descriptor Write Back interrupt. Reserved 9:8 0b Reserved. Write 0b, ignore on read. GPHY 10 0b Clears the mask for the Internal 1000/100/10BASE-T PHY interrupt.
Programming Interface — Ethernet Controller I210 8.8.14 Interrupt Throttle - EITR (0x1680 + 4*n [n = 0...4]; R/W) Each EITR is responsible for an interrupt cause (RxTxQ, TCP timer and Other Cause). The allocation of EITR-to-interrupt cause is through the IVAR registers. Software uses this register to pace (or even out) the delivery of interrupts to the host processor.
Ethernet Controller I210 — Programming Interface 8.8.15 Interrupt Vector Allocation Registers - IVAR (0x1700 + 4*n [n=0...1]; RW) These registers have two modes of operation: 1. In MSI-X mode, these registers define the allocation of the different interrupt causes as defined in Table 7-50 to one of the MSI-X vectors. Each INT_Alloc[i] (i=0...7) field is a byte indexing an entry in the MSI-X Table Structure and MSI-X PBA Structure. 2.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description INT_Alloc[9] 10:8 0x0 Defines the MSI-X vector assigned to the Other Cause interrupt. Valid values are 0 to 4. Reserved 14:11 0x0 Reserved. Write 0x0, ignore on read. INT_Alloc[9] 15 0b Valid bit for INT_Alloc[9]. Reserved 31:16 0x0 Reserved. Write 0x0, ignore on read. 8.8.
Ethernet Controller I210 — Programming Interface The pending bit array register indicates which vectors have pending interrupts. The structure is listed in Table 8-22. Table 8-22.
Programming Interface — Ethernet Controller I210 8.9.3 MSI-X Table Entry Message - MSIXTMSG (BAR3: 0x0008 + 0x10*n [n=0...4]; R/W) Field Message Data Bit(s) 31:0 8.9.4 Initial Value 0x0 Description System-Specific Message Data. For MSI-X messages, the contents of this field from an MSI-X table entry specifies the data written during the memory write transaction. In contrast to message data used for MSI messages, the low-order message data bits in MSI-X messages are not modified by the function.
Ethernet Controller I210 — Programming Interface 8.10 Receive Register Descriptions 8.10.1 Receive Control Register - RCTL (0x0100; R/W) Field Reserved RXEN SBP Bit(s) 0 1 2 Initial Value Description 0b Reserved. Write 0b, ignore on read. 0b Receiver Enable. The receiver is enabled when this bit is set to 1b. Writing this bit to 0b stops reception after receipt of any in progress packet. All subsequent packets are then immediately dropped until this bit is set to 1b.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description MO 13:12 00b Multicast Offset. Determines which bits of the incoming multicast address are used in looking up the bit vector. 00b = bits [47:36] of received destination multicast address. 01b = bits [46:35] of received destination multicast address. 10b = bits [45:34] of received destination multicast address. 11b = bits [43:32] of received destination multicast address. Reserved 14 0b Reserved.
Ethernet Controller I210 — Programming Interface Field Reserved SECRC Bit(s) 25:24 26 Initial Value 0x0 0b Description Reserved. Write 0x0, ignore on read. Strip Ethernet CRC From Incoming Packet Causes the CRC to be stripped from all packets. 0b = Does not strip CRC. 1b = Strips CRC. This bit controls whether the hardware strips the Ethernet CRC from the received packet. This stripping occurs prior to any checksum calculations.
Programming Interface — Ethernet Controller I210 Field Reserved Timestamp Drop_En Bit(s) 29:28 30 31 8.10.3 Initial Value Description 0x0 Reserved. Write 0x0, ignore on read. 0b Timestamp Received Packet 0b = Do not place timestamp at the beginning of a receive buffer. 1= Place timestamp at the beginning of a receive buffer. Timestamp is placed only in buffers of received packets that meet the criteria defined in the TSYNCRXCTL.Type field, 2-tuple filters or ETQF registers.
Ethernet Controller I210 — Programming Interface Field Bit(s) Reserved_1 16 Initial Value Description Reserved. Write 1b, ignore on read. 1b PSR_type17 17 1b Header includes MAC, (VLAN/SNAP) IPv6, TCP, NFS only. PSR_type18 18 1b Header includes MAC, (VLAN/SNAP) IPv6, UDP, NFS only. Reserved 31:19 0x0 Reserved. Write 0b, ignore on read. 8.10.4 Receive Descriptor Base Address Low - RDBAL (0xC000 + 0x40*n [n=0...
Programming Interface — Ethernet Controller I210 Field1 Bit(s) Initial Value Description Ignore on writes. Bits 6:0 must be set to 0x0. Bits 4:0 always read as 0x0. Zero 6:0 0x0 LEN 19:7 0x0 Note: Reserved 31:20 0x0 Reserved. Write 0x0, ignore on read. Descriptor Ring Length (number of 8 descriptor sets). Maximum allowed value in RDLEN field 19:0 is 0x80000 (32K descriptors). 1. Software should program the RDLEN[n] register only when a queue is disabled (RXDCTL[n].Enable = 0b). Note: 8.
Ethernet Controller I210 — Programming Interface 8.10.9 Receive Descriptor Control - RXDCTL (0xC028 + 0x40*n [n=0...3]; R/W) This register controls the fetching and write-back of receive descriptors. The three threshold values are used to determine when descriptors are read from and written to host memory. The values are in units of descriptors (each descriptor is 16 bytes).
Programming Interface — Ethernet Controller I210 Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are aliased to addresses 0x2828, 0x2928, 0x2A28 and 0x2B28, respectively. 8.10.10 Field Receive Queue Drop Packet Count - RQDPC (0xC030 + 0x40*n [n=0...3]; RW) Bit(s) RQDPC 31:0 Initial Value 0x0 Description Receive Queue Drop Packet Count. Counts the number of packets dropped by a queue due to lack of descriptors available.
Ethernet Controller I210 — Programming Interface Field PCSS Bit(s) 7:0 Initial Value 0x0 Description Packet Checksum Start. Controls the packet checksum calculation. The packet checksum shares the same location as the RSS field and is reported in the receive descriptor when the RXCSUM.PCSD bit is cleared. If the RXCSUM.IPPCSE is set, the Packet checksum is aimed to accelerate checksum calculation of fragmented UDP packets. Please refer to Section 7.1.7.2 for detailed explanation. If RXCSUM.
Programming Interface — Ethernet Controller I210 8.10.13 Field Receive Long Packet Maximum Length - RLPML (0x5004; R/W) Bit(s) Initial Value Description RLPML 13:0 0x2600 Maximum allowed long packet length. This length is the global length of the packet including all the potential headers of suffixes in the packet. Reserved 31:14 0x0 Reserved. Write 0x0, ignore on read. 8.10.
Ethernet Controller I210 — Programming Interface Field Bit(s) Bit Vector 31:0 Initial Value X Description Word wide bit vector specifying 32 bits in the multicast address filter table. Figure 8-1 shows the multicast lookup algorithm. The destination address shown represents the internally stored ordering of the received DA. Note that bit 0 indicated in this diagram is the first on the wire. Destination Address 47:40 39:32 31:24 23:16 15:8 7:0 RCTL.
Programming Interface — Ethernet Controller I210 8.10.17 Receive Address High - RAH (0x5404 + 8*n [n=0...15]; R/W) These registers contain the upper bits of the 48-bit Ethernet address. The complete address is [RAH, RAL]. The RAH.AV bit determines whether this address is compared against the incoming packet. The RAH.ASEL field enables the I210 to perform special filtering on receive packets.
Ethernet Controller I210 — Programming Interface 8.10.18 VLAN Priority Queue Filter VLAPQF (0x55B0;R/W) Field Bit(s) Initial Value Description VLAN Priority 0 Queue Selection. This field defines the target queue for packets with VLAN priority value of 0x0 and are enabled by VLANPV. VP0QSEL 1:0 0x0 Reserved 2 0x0 Reserved. VLANP0V 3 0x0 VLAN Priority 0 Valid. This field enables VLAN Priority 0x0 for queue selection. VP1QSEL 5:4 0x0 VLAN Priority 1Queue Selection.
Programming Interface — Ethernet Controller I210 8.10.19 VLAN Filter Table Array - VFTA (0x5600 + 4*n [n=0...127]; R/W) There is one register per 32 bits of the VLAN Filter Table. The size of the word array depends on the number of bits implemented in the VLAN Filter Table. Software must mask to the desired bit on reads and supply a 32-bit word on writes. Note: All accesses to this table must be 32 bit.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description Def_Q 5:3 0x0 Defines the default queue according to value of the Multiple Receive Queues Enable field. If Multiple Receive Queues Enable equals: 000b= Def_Q defines the destination of all packets not forwarded by filters. 001b= Def_Q field is ignored 010b= Def_Q defines the destination of all packets not forwarded by RSS or filters. 011b = Def_Q field is ignored. 100-101b= Def_Q field is ignored.
Programming Interface — Ethernet Controller I210 8.10.22 Redirection Table - RETA (0x5C00 + 4*n [n=0...31]; R/W) The redirection table is a 128-entry table with each entry being eight bits wide. Only 1 to 3 bits of each entry are used to store the queue index. The table is configured through the following R/W registers. Field Bit(s) Initial Value Description Entry 0 7:0 0x0 Determines the tag value and physical queue for index 4*n+0 (n=0...31).
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description Reserved 28:0 0x0 Reserved. Write 0x0, ignore on read. Hide VLAN 29 0b If this bit is set, a value of zero is written in the RDESC.VLAN tag and in the RDESC.STATUS.VP fields of the received descriptor. If this bit is set for a queue, the DVMOLR.STRVLAN bit for this queue should be set also. STRVLAN 30 0b VLAN Strip.
Programming Interface — Ethernet Controller I210 Field Bit(s) Destination Port 15:0 Initial Value 0x0 Description Destination TCP Port This field is compared with the Destination TCP port in incoming packets. Only a packet with a matching destination TCP port triggers an immediate interrupt (if IMIR[n].Immediate Interrupt is set to 1b) and trigger the actions defined in the appropriate TTQF[n] register if all other filtering conditions are met. Note: Enabled by the IMIR.PORT_BP bit.
Ethernet Controller I210 — Programming Interface Field CtrlBit Bit(s) 18:13 Initial Value Description Control Bit. Defines TCP control bits used to generate immediate interrupt and trigger filter. Only a received packet with the corresponding TCP control bits set to 1b triggers an immediate interrupt (if IMIR[n].Immediate Interrupt is set to 1b) and trigger the actions defined in the appropriate TTQF[n] register (if TTQF[n].Queue Enable is set to 1b) if all other filtering conditions are met.
Programming Interface — Ethernet Controller I210 8.11.4 Immediate Interrupt Rx VLAN Priority - IMIRVP (0x5AC0; R/W) Field Bit(s) Initial Value Description Vlan_Pri 2:0 000b VLAN Priority. This field includes the VLAN priority threshold. When Vlan_pri_en is set to 1b, then an incoming packet with a VLAN tag with a priority field equal or higher to VlanPri triggers an immediate interrupt, regardless of the EITR moderation. Vlan_pri_en 3 0b VLAN Priority Enable.
Ethernet Controller I210 — Programming Interface Field Bit(s) Immediate Interrupt 29 Initial Value 0x0 1588 time stamp 30 0b Queue Enable 31 0b Description When set, packets that match this filter generate an immediate interrupt. When set, packets with this EType are time stamped according to the IEEE 1588 specification. Note: The packet is time stamped only if it matches IEEE 1588 protocol according to the definition in the TSYNCRXCTL.Type field.
Programming Interface — Ethernet Controller I210 Field Reserved Bit(s) 23 Initial Value 0b Description Reserved. Re-transmit on Late Collision. When set, enables the I210 to re-transmit on a late collision event. Note: RTLC 24 Reserved 31:25 8.12.2 0b RTLC configures the I210 to perform re-transmission of packets when a late collision is detected. Note that the collision window is speed dependent: 64 bytes for 10/100 Mb/s and 512 bytes for 1000 Mb/s operation.
Ethernet Controller I210 — Programming Interface Field IPGT IPGR1 Bit(s) 9:0 19:10 Initial Value Description 0x08 IPG Back to Back. Specifies the IPG length for back to back transmissions in both full and half duplex. Measured in increments of the MAC clock: 8 ns MAC clock when operating @ 1 Gb/s. 80 ns MAC clock when operating @ 100 Mb/s. 800 ns MAC clock when operating @ 10 Mb/s. IPGT specifies the IPG length for back-to-back transmissions in both full duplex and half duplex.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description Reserved 1:0 0x0 Reserved. Write 0x0, ignore on read. Enable_spoof_queue 2 0b Enable Spoofing Queue. 0b = Disable queue that exhibited spoofing behavior. 1b = Do not disable port that exhibited spoofing behavior. Reserved 3 0x0 Reserved. Write 0x0, ignore on read. OutOfSyncDisable 4 0b Disable Out Of Sync Mechanism. 0b = Out Of Sync mechanism is enabled. 1b = Out Of Sync mechanism is disabled.
Ethernet Controller I210 — Programming Interface 8.12.8 DMA TX Max Total Allow Size Requests - DTXMXSZRQ (0x3540; RW) This register limits the allowable size of concurrent outstanding Tx read requests from the host memory on the PCIe. Limiting the size of concurrent outstanding PCIe requests allows low latency packet read requests to be serviced in a timely manner, as the low latency request is serviced right after current outstanding requests are completed.
Programming Interface — Ethernet Controller I210 8.12.11 Transmit Descriptor Base Address High - TDBAH (0xE004 + 0x40*n [n=0...3]; R/W) These registers contain the upper 32 bits of the 64-bit descriptor base address. Field1 Bit(s) TDBAH 31:0 Initial Value X Description Transmit Descriptor Base Address [63:32]. 1. Software should program the TDBAH[n] register only when a queue is disabled (TXDCTL[n].Enable = 0b).
Ethernet Controller I210 — Programming Interface 8.12.14 Transmit Descriptor Tail - TDT (0xE018 + 0x40*n [n=0...3]; R/ W) These registers contain the tail pointer for the transmit descriptor ring and points to a 16-byte datum. Software writes the tail pointer to add more descriptors to the transmit ready queue. Hardware attempts to transmit all packets referenced by descriptors between head and tail.
Programming Interface — Ethernet Controller I210 Field WTHRESH Bit(s) 20:16 Initial Value 0x0 Description Write-Back Threshold. Controls the write-back of processed transmit descriptors. This threshold refers to the number of transmit descriptors in the on-chip buffer that are ready to be written back to host memory. In the absence of external events (explicit flushes), the write-back occurs only after at least WTHRESH descriptors are available for write-back.
Ethernet Controller I210 — Programming Interface 8.12.16 Tx Descriptor Completion Write-Back Address Low - TDWBAL (0xE038 + 0x40*n [n=0...3]; R/W) Field1 Bit(s) Initial Value Description Head Write-Back Enable. 1b = Head write back is enabled. 0b = Head write back is disabled. When head_WB_en is set, TXDCTL.SWFLSH is ignored and no descriptor write back is executed. Head_WB_En 0 0b WB_on_EITR 0b When set, a head write back is done upon EITR expiration.
Programming Interface — Ethernet Controller I210 8.12.19 Tx Qav Credit Control TQAVCC (0x3004 + 0x40*n [n=0...1]; R/ W) Field Bit(s) Initial Value IdleSlope. Idle Slope for this queue Value in credits. Must be smaller than LinkRate = 0x7735 credits/byte. See Section 7.2.7.6 for a description of how this field should be calculated. Relevant only if TransmitMode is set to 1b (Qav). IdleSlope 15:0 Reserved 29:16 0x0 Reserved. Reserved 30 0x0 Reserved. QueueMode 8.12.20 31 0x0 Queue Mode.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description DataTranARB 8 0x0 Data Transmit Arbitration. 0b = Strict Priority. 1b = Credit Shaper Algorithm. Relevant only if TransmitMode is set to 1b (Qav). DataTranTIM 9 0x0 Data Launch Time Valid. Relevant only if TransmitMode is set to 1b (Qav). SP_WAIT_SR 10 0x0 When set to 1b, the SP queues wait for the SR queues to make sure the SR launch time is always guaranteed. Reserved 15:11 0x0 Reserved.
Programming Interface — Ethernet Controller I210 Field RXdescRead NSEn Bit(s) 8 Initial Value 0b Description Receive Descriptor Read No Snoop Enable. This bit must be reset to 0b to ensure correct functionality (except if the software driver can guarantee the data is present in the main memory before the DMA process occurs). Note: When TPH is enabled, the No Snoop bit should be 0b. RXdescRead ROEn 9 1b Receive Descriptor Read Relax Order Enable.
Ethernet Controller I210 — Programming Interface 8.13.2 Tx DCA Control Registers - TXCTL (0xE014 + 0x40*n [n=0...3]; R/W) Field Bit(s) Initial Value Description Tx Descriptor Fetch TPH EN1 0 0b Transmit Descriptor Fetch TPH Enable. When set, hardware enables TPH for all Tx descriptors fetch from memory. When cleared, hardware does not enable TPH for descriptor fetches. This bit is cleared as a default. Tx Descriptor Writeback TPH EN 1 0b Transmit Descriptor Writeback TPH Enable.
Programming Interface — Ethernet Controller I210 Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are aliased to addresses 0x3814, 0x3914, 0x3A14 and 0x3B14, respectively. 8.13.3 DCA Requester ID Information - DCA_ID (0x5B70; RO) The DCA Requester ID field, composed of Device ID, Bus #, and Function # is set up in MMIO space for software to program the DCA Requester ID Authentication register.
Ethernet Controller I210 — Programming Interface 8.14 Timer Registers Description 8.14.1 Watchdog Setup - WDSTP (0x1040; R/W) Field Bit(s) WD_Enable Initial Value 1 0 0b WD_Timer_ Load_enable (SC) 1 0b Reserved 15:2 0x0 WD_Timer (RWM) 23:16 WD_Timeout Description Enable Watchdog Timer. Enables the load of the watchdog timer by writing to WD_Timer field. If this bit is not set, the WD_Timer field is loaded by the value of WD_Timeout. Note: Reserved. Write 0x0, ignore on read.
Programming Interface — Ethernet Controller I210 Field Bit(s) Microsecond Initial Value 9:0 X Description Number of microseconds in the current millisecond. Millisecond 19:10 X Number of milliseconds in the current second. Seconds 31:20 X Number of seconds from the timer start (up to 4095 seconds). 8.14.4 TCP Timer - TCPTIMER (0x104C; R/W) Field Bit(s) Initial Value Description Duration 7:0 0x0 Duration. Duration of the TCP interrupt interval in ms.
Ethernet Controller I210 — Programming Interface 8.15 Time Sync Register Descriptions 8.15.1 Rx Time Sync Control Register - TSYNCRXCTL (0xB620;RW) Field Bit(s) Initial Value RXTT(RO) 0 0x0 Rx Timestamp Valid Bit is set when a valid value for Rx timestamp is captured in the Rx timestamp registers. Bit is cleared by read of Rx timestamp high register (RXSTMPH)). Type of Packets to Timestamp.
Programming Interface — Ethernet Controller I210 8.15.4 Tx Time Sync Control Register - TSYNCTXCTL (0xB614; RW) Field Bit(s) Initial Value Description TXTT(ROM) 0 0b Transmit timestamp valid (equals 1b when a valid value for Tx timestamp is captured in the Tx timestamp register, clear by read of Tx timestamp register TXSTMPH). RSV 3:1 0x0 EN 4 0b RSV 5:7 0x0 Reserved. Write 0x0, ignore on read.
Ethernet Controller I210 — Programming Interface 8.15.9 System Time Register High - SYSTIMH (0xB604; RW) Field Bit(s) Initial Value STH 31:0 0x0 8.15.10 Field Description System time MSB value (defined in sec units). System Time Register Tx MS - SYSTIMTM (0xB6FC; RW) Bit(s) Initial Value Description STM 15:0 0x0 Two MS bytes of the system time (defined in 232 sec units). This field is static, kept at the value programmed by the software.
Programming Interface — Ethernet Controller I210 8.15.13 TimeSync Auxiliary Control Register - TSAUXC (0xB640; RW) Field Bit(s) Initial Value EN_TT0 0 0b EN_TT1 1 0b Description Enable target time 0. Enable bit is set by software to 1b, to enable pulse or level change generation as a function of the TSAUXC.PLSG bit. Enable target time 1. Enable bit is set by software to 1b, to enable a level change. EN_CLK0 2 0b Enable Configurable Frequency Clock 0.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Reserved 29:18 0b Reserved. Write 0b, ignore on read. Reserved 30 1b Reserved. Write 1b, ignore on read. Disable systime 31 1b Disable SYSTIM Count Operation. 0b = SYSTIM timer activated 1b = SYSTIM timer disabled. Value of SYSTIMH, SYSTIML and SYSTIMR remains constant. 8.15.
Programming Interface — Ethernet Controller I210 8.15.18 Field Frequency Out 0 Control Register FREQOUT0 (0xB654; RW) Bit(s) Initial Value Description CHCT 29:0 0x0 Clock Out Half Cycle Time. Defines the Half Cycle time of Clock 0 in ns units. When clock output is enabled, permitted values are any value larger than 8 and up to including 70,000,000 decimal (70 ms).
Ethernet Controller I210 — Programming Interface 8.15.23 Auxiliary Time Stamp 1 Register High - AUXSTMPH1 (0xB668; RO) Reading this register releases the value stored in AUXSTMPH/L1 and enables timestamping of the next value. Field Bit(s) Initial Value TSTH 31:0 0x0 8.15.24 Field Description Auxiliary Time Stamp 1 MSB value (defined in second units). Time Sync RX Configuration - TSYNCRXCFG (0x5F50; R/W) Bit(s) Initial Value CTRLT 7:0 0x0 MSGT 15:8 0x0 V2 Message Type to timestamp.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description TS_SDP1_SEL 10:9 00b SDP1 allocation to Tsync event – when TS_SDP1_EN is set, these bits select the Tsync event that is routed to SDP1. 00b = Target time 0 is output on SDP1. 01b = Target time 1 is output on SDP1. 10b = Freq clock 0 is output on SDP1. 11b = Freq clock 1 is output on SDP1. TS_SDP1_EN 11 0b When set indicates that SDP1 is assigned to Tsync.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value AUTT1 6 0b Auxiliary Timestamp 1 Taken. Set when new timestamp is loaded into AUXSTMP 1 (auxiliary timestamp 1) register. TADJ 7 0b Time Adjust Done. Set when time adjust-to-SYSTIM completes. Reserved 31:8 0x0 8.16.2 Field Description Reserved. Write 0x0, ignore on read. Time Sync Interrupt Mask Register - TSIM (0xB674; RW) Bit(s) Initial Value Description SYS WARP 0 0b SYSTIM Warp Around Mask.
Programming Interface — Ethernet Controller I210 8.17.1 PCS Configuration - PCS_CFG (0x4200; R/W) Field Reserved Bit(s) 2:0 Initial Value Description 0x0 Reserved. Write 0x0, ignore on read. PCS Enable 3 1b PCS Enable. Enables the PCS logic of the MAC. Should be set in SGMII, 1000BASE-KX and SerDes mode for normal operation. Clearing this bit disables Rx/Tx of both data and control codes. Use this to force link down at the far end. Reserved 29:4 0x0 Reserved. Write 0x0, ignore on read.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description Force Flow Control 7 0b 0b = Flow control mode is set according to the AN process by following Table 37-4 in the IEEE 802.3 specification. 1b = Flow control is set according to FC_TX_EN / FC_RX_EN bits in CTRL register. Reserved 15:8 0x0 Reserved. Write 0x0, ignore on read. AN_ENABLE 16 0b1 AN Enable. Setting this bit enables the AN process in SerDes operating mode.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description SYNC OK 4 0b Sync OK. This bit indicates the current value of Sync OK from the PCS Sync state machine. Reserved 15:5 0x0 Reserved. Write 0x0, ignore on read. AN COMPLETE 16 0b AN Complete. This bit indicates that the AN process has completed.This bit is set when the AN process reached the Link OK state. It is reset upon AN restart or reset.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description RFLT 13:12 00b Remote Fault. The I210's remote fault condition is encoded in this field. The I210 might indicate a fault by setting a non-zero remote fault encoding and re-negotiating. 00b = No error, link OK. 01b = Link failure. 10b = Offline. 11b = Auto-negotiation error. Reserved 14 0x0 Reserved. Write 0x0, ignore on read. NEXTP 15 0b Next Page Capable.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description ACK 14 0b Acknowledge (SerDes). The link partner has acknowledged receiving a page. SGMII: Reserved. LPNEXTP 15 0b LP Next Page Capable (SerDes). The link partner asserts this bit to indicate its ability to accept next pages. SGMII: Link OK indication from the PHY. Reserved 31:16 0x0 Reserved. Write 0x0, ignore on read. 8.17.
Ethernet Controller I210 — Programming Interface 8.17.7 Link Partner Ability Next Page - PCS_LPABNP (0x4224; RO) Field CODE Bit(s) 10:0 Initial Value Description - Message/Unformatted Code Field. The Message field is an 11-bit wide field that encodes 2048 possible messages. The Unformatted Code field is an 11-bit wide field that might contain an arbitrary value. TOGGLE 11 - Toggle. This bit is used to ensure synchronization with the link partner during next page exchange.
Programming Interface — Ethernet Controller I210 Field DATA Bit(s) 15:0 Initial Value X Description Data. In a Write command, software places the data bits and then the MAC shifts them out to the I2C bus. In a Read command, the MAC reads these bits serially from the I2C bus and then software reads them from this location. Note: This field is read in byte order and not in word order. REGADD 23:16 0x0 I2C Register Address. For example, register 0, 1, 2... 255.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description I2C_DATA. DATA_OUT 10 0b While in bit-bang mode and when the DATA_OE_N field is zero, controls the value driven on the I2C_DATA pad. DATA_OE_N 11 0b I2C_DATA_OE_N. While in bit-bang mode, controls the direction of the I2C_DATA pad. 0b = Pad is output. 1b = Pad is input. DATA_IN (RO) 12 X I2C_DATA_IN. Reflects the value of the I2C_DATA pad.
Programming Interface — Ethernet Controller I210 8.18.2 Alignment Error Count - ALGNERRC (0x4004; RC) Counts the number of receive packets with alignment errors (the packet is not an integer number of bytes in length). In order for a packet to be counted in this register, it must pass address filtering and must be 64 bytes or greater (from through , inclusive) in length. If receives are not enabled, then this register does not increment.
Ethernet Controller I210 — Programming Interface 8.18.6 Single Collision Count - SCC (0x4014; RC) This register counts the number of times that a successfully transmitted packet encountered a single collision. This register only increments if transmits are enabled (TCTL.EN is set) and the I210 is in halfduplex mode. Field SCC Bit(s) 31:0 8.18.7 Initial Value 0x0 Description Number of times a transmit encountered a single collision.
Programming Interface — Ethernet Controller I210 8.18.11 Defer Count - DC (0x4030; RC) This register counts defer events. A defer event occurs when the transmitter cannot immediately send a packet due to the medium being busy either because another device is transmitting, the IPG timer has not expired, half-duplex deferral events, reception of XOFF frames, or the link is not up. This register only increments if transmits are enabled (TCTL.EN is set).
Ethernet Controller I210 — Programming Interface Field RLEC 8.18.15 Bit(s) 31:0 Initial Value 0x0 Description Number of packets with receive length errors. XON Received Count - XONRXC (0x4048; RC) This register counts the number of valid XON packets received. XON packets can use the global address, or the station address. This register only increments if receives are enabled (RCTL.RXEN is set). Field XONRXC 8.18.16 Bit(s) 31:0 Initial Value 0x0 Description Number of XON packets received.
Programming Interface — Ethernet Controller I210 The FCRUC counter increments when a flow control packet is received that matches either the reserved flow control multicast address (in the FCAH/L register) or the MAC station address, and has a matching flow control type field match (value in the FCT register), but has an incorrect op-code field. This register only increments if receives are enabled (RCTL.RXEN is set). Note: When the RCTL.
Ethernet Controller I210 — Programming Interface 8.18.23 Packets Received [256–511 Bytes] Count - PRC511 (0x4068; RC) This register counts the number of good packets received that are 256-511 bytes (from through , inclusive) in length. Packets that are counted in the Missed Packet Count register are not counted in this register. Packets sent to the manageability engine are included in this counter.
Programming Interface — Ethernet Controller I210 Note: GPRC can count packets interrupted by a link disconnect although they have a CRC error. Field GPRC 8.18.27 Bit(s) 31:0 Initial Value 0x0 Description Number of good packets received (of any length). Broadcast Packets Received Count - BPRC (0x4078; RC) This register counts the number of good (no errors) broadcast packets received. This register does not count broadcast packets received when the broadcast address filter is disabled.
Ethernet Controller I210 — Programming Interface These octets do not include octets of received flow control packets. Field GORCL 8.18.31 Bit(s) 31:0 8.18.32 0x0 Description Number of good octets received ‚Äì lower 4 bytes. Good Octets Received Count - GORCH (0x408C; RC) Field GORCH Initial Value Bit(s) 31:0 Initial Value 0x0 Description Number of good octets received ‚Äì upper 4 bytes.
Programming Interface — Ethernet Controller I210 8.18.35 Receive Undersize Count - RUC (0x40A4; RC) This register counts the number of received frames that passed address filtering, and were less than minimum size (64 bytes from through , inclusive), and had a valid CRC. This register only increments if receives are enabled (RCTL.RXEN is set). Packets sent to the manageability engine are included in this counter.
Ethernet Controller I210 — Programming Interface If receives are not enabled, this register does not increment. These lengths are based on bytes in the received packet from through , inclusive. Packets sent to the manageability engine are included in this counter. Field RJC Bit(s) 31:0 8.18.39 Initial Value 0x0 Description Number of receive jabber errors.
Programming Interface — Ethernet Controller I210 8.18.43 BMC2OS Packets Received by Host - B2OGPRC (0x4158; RC) This register counts the total number of packets originating from the MC that reached the host. If a packet is replicated, this counter counts each replication of the packet. The counter clears when read by the software device driver. The counter also clears by a PCIe reset and software reset. When reaching the maximum, the value counter does not wrap-around. Field Bit(s) B2OGPRC 31:0 8.18.
Ethernet Controller I210 — Programming Interface Field TORL 8.18.47 Bit(s) 31:0 8.18.48 Description Number of total octets received - lower 4 bytes. Total Octets Received - TORH (0x40C4; RC) Field TORH Initial Value 0x0 Bit(s) 31:0 Initial Value 0x0 Description Number of total octets received - upper 4 bytes. Total Octets Transmitted - TOTL (0x40C8; RC) These registers make up a 64-bit register that counts the total number of octets transmitted.
Programming Interface — Ethernet Controller I210 8.18.51 Total Packets Transmitted - TPT (0x40D4; RC) This register counts the total number of all packets transmitted. All packets transmitted are counted in this register, regardless of their length, or whether they are flow control packets. Partial packet transmissions (collisions in half-duplex mode) are not included in this register. This register only increments if transmits are enabled (TCTL.EN is set).
Ethernet Controller I210 — Programming Interface 8.18.55 Packets Transmitted [256-511 Bytes] Count - PTC511 (0x40E4; RC) This register counts the number of packets transmitted that are 256-511 bytes (from through , inclusive) in length. Partial packet transmissions (for example, collisions in half-duplex mode) are not included in this register. This register only increments if transmits are enabled (TCTL.EN is set). This register counts all packets.
Programming Interface — Ethernet Controller I210 8.18.59 Broadcast Packets Transmitted Count - BPTC (0x40F4; RC) This register counts the number of broadcast packets transmitted. This register only increments if transmits are enabled (TCTL.EN is set). This register counts all packets. Management packets must never be more than 200 bytes. Field BPTC 8.18.60 Bit(s) 31:0 Initial Value 0x0 Description Number of broadcast packets transmitted count.
Ethernet Controller I210 — Programming Interface 8.18.64 Host Good Packets Transmitted Count-HGPTC (0x4118; RC) Field HGPTC Bit(s) Initial Value 31:0 0x0 Description Number of good packets transmitted by the host. This register counts the number of good (non-erred) packets transmitted sent by the host. A good transmit packet is considered one that is 64 or more bytes in length (from through , inclusively) in length.
Programming Interface — Ethernet Controller I210 8.18.68 Field HGOTCL 8.18.69 Field HGOTCH Host Good Octets Transmitted Count - HGOTCL (0x4130; RC) Bit(s) 31:0 Initial Value 0x0 Description Number of good octets transmitted by host - lower 4 bytes. Host Good Octets Transmitted Count - HGOTCH (0x4134; RC) Bit(s) 31:0 Initial Value 0x0 Description Number of good octets transmitted by host - upper 4 bytes.
Ethernet Controller I210 — Programming Interface 8.18.72 Field MNGFDPC Management Full Buffer Drop Packet Count - MNGFBDPC (0x4154; RC/W) Bit(s) 31:0 Initial Value Description Management Buffer Full Drop Packet Count. Counts the number of packets destined to management that were dropped due to lack of space in the management buffer. 0x0 Note: 8.19 The counter does not wrap around when reaching a value of 0xFFFFFFFF. Statistical Counters The I210 supports nine statistical counters per queue.
Programming Interface — Ethernet Controller I210 8.19.3 Per Queue Good Octets Received Count - PQGORC (0x10018 + n*0x100 [n=0...3]; RW) This register counts the number of good (no errors) octets received on queue[n]. This register includes bytes received in a packet from the field through the field, inclusive. Only octets of packets that pass address filtering are counted in this register. This register only increments if receive is enabled.
Ethernet Controller I210 — Programming Interface Field MPRC 8.20 Bit(s) 31:0 Initial Value 0x0 Description Number of multicast packets received. Manageability Statistics This section describes a set of statistics counters used by the NC-SI interface and are not accessible to the host driver. 8.20.1 MC Management Receive Packets Dropped Count - BMRPDC (0x4140; RC) This register counts the total number of packets received that pass the management filters as described in Section 10.
Programming Interface — Ethernet Controller I210 8.20.4 MC Management Packets Received Count - BMNGPRC (0x413C; RC) This register counts the total number of packets received that pass the management filters as described in Section 10.3. Any packets with errors are not counted, except packets that are dropped because the management receive FIFO is full. This register is available to the firmware only. Field MNGPRC 8.20.5 Bit(s) 31:0 Initial Value 0x0 Description Number of management packets received.
Ethernet Controller I210 — Programming Interface 8.20.10 MC Total Broadcast Packets Transmitted - BBPTC (0x4414; RC) This register counts the same events as the BPTC register (Section 8.18.59) for the MC usage. This register is available to the firmware only. 8.20.11 MC FCS Receive Errors - BCRCERRS (0x4418; RC) This register counts the same events as the CRCERRS register (Section 8.18.1) for the MC usage. This register is available to the firmware only. 8.20.
Programming Interface — Ethernet Controller I210 8.21 Wake Up Control Register Descriptions 8.21.1 Wake Up Control Register - WUC (0x5800; R/W) The PME_En and PME_Status bits of this register are reset when LAN_PWR_GOOD is 0b. When AUX_PWR = 0b, these register bits also reset by de-asserting PE_RST_N and during a D3 to D0 transition. Field APME Bit(s) 0 Initial Value 0b1 Description Advance Power Management Enable. If set to 1b, APM Wakeup is enabled.
Ethernet Controller I210 — Programming Interface 8.21.2 Wakeup Filter Control Register - WUFC (0x5808; R/W) This register is used to enable each of the pre-defined and flexible filters for wake-up support. A value of 1b means the filter is turned on; A value of 0b means the filter is turned off. If the NoTCO bit is set, then any packet that passes the manageability packet filtering as described in Section 10.3, does not cause a wake-up event.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description FLX2_ACT 26 0b Flexible Filter 2 Action. 0b= WoL. 1b= Reserved. FLX3_ACT 27 0b Flexible Filter 3 Action. 0b= WoL. 1b= Reserved. Reserved 30:28 0b Reserved. 0b Enable Wake on Firmware Reset Assertion. When set, a firmware reset causes a system wake so that the software driver can re-send proxying information to firmware. FW_RST_WK 31 1. If the RCTL.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value Description Reserved 15:12 0x0 Reserved. Write 0bx0, ignore on read. FLX0 16 0b Flexible Filter 0 Match. FLX1 17 0b Flexible Filter 1 Match. FLX2 18 0b Flexible Filter 2 Match. FLX3 19 0b Flexible Filter 3 Match. FLX4 20 0b Flexible Filter 4 Match. FLX5 21 0b Flexible Filter 5 Match. FLX6 22 0b Flexible Filter 6 Match. FLX7 23 0b Flexible Filter 7 Match. Reserved 30:24 0x0 Reserved.
Programming Interface — Ethernet Controller I210 Field D0_PROXY Bit(s) 0 Initial Value 0b Description Enable Protocol Offload in D0. 0b = Enable protocol offload only when device is in D3 low power state. 1b = Enable protocol offload always. Note: Protocol offload is enabled only when the WUC.PPROXYE and MANC.MPROXYE bits are set to 1b. Reserved 1 0b Reserved. Write 0b, ignore on read. EX 2 0b Directed Exact Proxy Enable.1 MC 3 0b Directed Multicast Proxy Enable.
Ethernet Controller I210 — Programming Interface 8.21.7 Proxying Status Register - PROXYS (0x5F64; R/W1C) This register is used to record statistics about all proxying packets received. If a packet matches multiple criteria then multiple bits could be set. Writing a 1b to any bit clears that bit. This register is not cleared when PE_RST_N is asserted. It is only cleared when LAN_PWR_GOOD is deasserted or when cleared by the software device driver.
Programming Interface — Ethernet Controller I210 8.21.8 Proxying Filter Control Extended Register - PROXYFCEX (0x5590; R/W) This register is an extension to PROXYFC and is used to control and enable the routing to management (like firmware) of a set of pre-defined and flexible filters and filter combinations for proxying support. Field Bit(s) Initial Value Description mDNS 0 0b Route to management if UDP and UDP port equals 5353.
Ethernet Controller I210 — Programming Interface Note: If additional packets are received that matches one of the wake-up filters, after the original wake-up packet is received, the PROXYS register is updated with the matching filters accordingly. Field Bit(s) Initial Value Description mDNS 0 0b mDNS matched. mDNS_mDirected 1 0b mDNS_mDirected matched. mDNS_uDirected 2 0b mDNS_uDirected matched. IPv4_mDirected 3 0b IPv4_mDirected matched. IPv6_mDirected 4 0b IPv6_mDirected matched.
Programming Interface — Ethernet Controller I210 Field Control Bit(s) 17:16 Initial Value Description 00b Flex Port Control. 00b = Port filter disabled. 01b = UDP port. 10b =TCP port. 11b = TCP port and TCP flag SYN set, TCP flag RESET clear. Action 18 0b The Action bit defines the action to take on a match to an enabled filter. 0b= Host wake up. 1b= Route to the MC. Routing to the MC is only enabled when proxy functionality is enabled and is not intended for pass through.
Ethernet Controller I210 — Programming Interface 8.21.13 Wake Flex UDP/TCP Ports Status - WFUTPS (0x5588, R/W1C) Field Bit(s) Initial Value Description Port0 0 0b Flex Port 0 matched. Port1 1 0b Flex Port 1 matched. Port2 2 0b Flex Port 2 matched. Port3 3 0b Flex Port 3 matched. Port4 4 0b Flex Port 4 matched. Port5 5 0b Flex Port 5 matched. Port6 6 0b Flex Port 6 matched. Port7 7 0b Flex Port 7 matched. Port8 8 0b Flex Port 8 matched.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description Reserved 29:4 0x0 Reserved. Write 0x0, ignore on read. LocalIPOrNameCo nflict 30 0b Local IP Conflict or Name Conflict Detected by Proxy. A firmware write of 1b sets the field, while a software write of 1b clears the field. Firmware writes to set are not blocked if other fields of the status are already set. mDNS Proxy Error Recovery 31 0b mDNS Proxy Error Recovery.
Ethernet Controller I210 — Programming Interface 8.21.17 IPv6 Address Table - IP6AT (0x5880 + 4*n [n=0...3]; R/W) The IPv6 address table is used to store the IPv6 addresses for neighbor discovery packet filtering and directed IP packet wake up. Field Bit(s) Initial Value Description IPv6 Address bytes 4*n+1:4*n +4. IP Address 31:0 Field X Dword # IPV6ADDR0 8.21.
Programming Interface — Ethernet Controller I210 Table 8-24. FHFT Filter Description 31 0 31 8 7 0 31 Mask [7:0] 0 31 DW 1 0 Reserved Reserved Dword 0 Reserved Reserved Mask [15:8] DW 3 Dword 2 Reserved Reserved Mask [23:16] DW 5 Dword 4 Reserved Reserved Mask [31:24] DW 7 Dword 6 ....
Ethernet Controller I210 — Programming Interface 8.21.18.2 Flex Filter 0 - Example Field Dword Address Bit(s) Initial Value Filter 0 DW0 0 0x9000 31:0 X Filter 0 DW1 1 0x9004 31:0 X Filter 0 Mask[7:0] 2 0x9008 7:0 X Reserved 3 0x900C 31:0 X Filter 0 DW2 4 0x9010 31:0 X ‚Ķ Filter 0 DW30 60 0x90F0 31:0 X Filter 0 DW31 61 0x90F4 31:0 X Filter 0 Mask[127:120] 62 0x90F8 7:0 X Length 63 0x90FC 7:0 X Filter 0 Queueing 63 0x90FC 31:8 X 8.21.
Programming Interface — Ethernet Controller I210 The MAVTV registers are written by the MC and are not accessible to the host for writing. The registers are used to filter manageability packets as described in the manageability chapter. 8.22.2 Management Flex UDP/TCP Ports - MFUTP (0x5030 + 4*n [n=0...7]; 0x5070 + 4*n [n=0...7]; RW) Where each 32-bit register (n=0...15) refers to one UDP/TCP port filters. Field Bit(s) Initial Value Description MFUTP port 15:0 0x0 Management Flex UDP/TCP port #n.
Ethernet Controller I210 — Programming Interface 8.22.4 Management Ethernet Type Filters- METF (0x5060 + 4*n [n=0...3]; RW) Field METF Bit(s) Initial Value 15:0 Description 0x0 EtherType value to be compared against the L2 EtherType field in the Rx packet. Reserved 29:16 0x0 Reserved. Write 0x0, ignore on read. Polarity 30 0b 0b = Positive filter - forward packets matching this filter to the manageability block.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description Block PHY reset and power state changes. When this bit is set, the PHY reset and power state changes do not effect the PHY, This bit can not be written to unless the Keep_PHY_Link_Up_En Flash bit is set. KEEP_PHY_LINK_UP 18 0b1 Reserved 0b Reserved. 19 Reserved 22:20 0b Reserved. Write 0b, ignore on read. EN_XSUM_FILTER 23 0b1 Enable Checksum Filtering to MNG.
Ethernet Controller I210 — Programming Interface Field Bit(s) EN_BMC2NET (RO) 29 Initial Value 1b1 Description Enable MC to network and network to MC traffic. 0b = The MC cannot communicate with the network. 1b = The MC can communicate with the network. When cleared, the MC traffic is not forwarded to the network and the network traffic is not forwarded to the MC even if the decision filters indicates it should. This bit does not impact the host-to-MC traffic. Note: 1.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value1 Description Exact AND 3:0 0x0 Exact. Controls the inclusion of exact MAC address 0 to 3. In the manageability filter decision (AND section). Bit 0 corresponds to exact MAC address 0 (MMAL0 and MMAH0), etc. Broadcast AND 4 0b Broadcast. Controls the inclusion of broadcast address filtering in the manageability filter decision (AND section). VLAN. Controls the inclusion of VLAN tag 0 to 7, respectively.
Ethernet Controller I210 — Programming Interface Field Bit(s) Initial Value1 Description Router Advertisement Discovery. Controls the inclusion of router advertisement filtering in the manageability filter decision (OR section). Neighbor Discovery -134 (Router Advertisement) 29 Port 0x298 Notes: 1. Supported only for network traffic. For host traffic, any IPv6 packet passes this filter. 2. Neighbor discovery types supported by this bit is 0x86 (134d) - router advertisement. 0b 30 Port 0x298.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value1 Description Neighbor Advertisement. Controls the inclusion of neighbor advertisement filtering in the manageability filter decision (OR section). Neighbor Discovery -136 (Advertisement) 26 Notes: 1. Supported only for network traffic. For host traffic, any IPv6 packet passes this filter. 2. Neighbor discovery types supported by this bit is 0x88 (136d) - neighbor advertisement. 0b Redirect Neighbor Discovery.
Ethernet Controller I210 — Programming Interface DWORD# Address 0 0x58B0 1 0x58B4 2 0x58B8 3 0x58BC 4 0x58C0 5 0x58C4 6 0x58C8 7 0x58CC 8 0x58D0 9 0x58D4 10 0x58D8 11 0x58DC 12 0x58E0 13 0x58E4 14 0x58E8 15 0x58EC 31 0 IPV6ADDR0 IPV6ADDR1 IPV6ADDR2 IPV6ADDR3 Field definitions for 0 setting: Field IPV6ADDR0 IPV6ADDR1 IPV6ADDR2 IPV6ADDR3 Dword # Address Bit(s) Initial Value 0 0x58B0 31:0 X* IPv6 Address 0, bytes 1-4 (LS byte is first on the wire).
Programming Interface — Ethernet Controller I210 DWORD# Address 0 0x58B0 1 0x58B4 2 0x58B8 3 0x58BC 4 0x58C0 5 0x58C4 6 0x58C8 7 0x58CC 8 0x58D0 31 0 IPV6ADDR0 IPV6ADDR1 9 0x58D4 10 0x58D8 11 0x58DC 12 0x58E0 IPV4ADDR0 13 0x58E4 IPV4ADDR1 14 0x58E8 IPV4ADDR2 15 0x58EC IPV4ADDR3 IPV6ADDR2 Field definitions for 1 setting: Dword # Address Bit(s) Initial Value1 0 0x58B0 31:0 X IPv6 Address 0, bytes 1-4 (LS byte is first on the wire).
Ethernet Controller I210 — Programming Interface Initial value: Field Initial Value1 Bit(s) IP_ADDR 4 bytes 31:0 Description 4 bytes of IP (v6 or v4) address. i mod 4 = 0 to bytes 1 - 4. i mod 4 = 1 to bytes 5 - 8. i mod 4 = 0 to bytes 9 - 12. i mod 4 = 0 to bytes 13 - 16. where i div 4 is the index of IP address (0...3). X 1. The initial values for these registers can be loaded from the Flash after power-up reset. The registers are written by the MC and not accessible to the host for writing.
Programming Interface — Ethernet Controller I210 These registers contain the upper bits of the 48-bit Ethernet address. The complete address is {MMAH, MMAL}. The MMAH registers are written by the MC and are not accessible to the host for writing. The registers are used to filter manageability packets. See Section 10.3. Reset - The MMAL registers are cleared on LAN_PWR_GOOD only. The initial values for this register can be loaded from the Flash after power-up reset or firmware reset. Note: The MMAH.
Ethernet Controller I210 — Programming Interface Table 8-25. FTFT Filter Description 31 0 31 8 7 0 31 0 31 0 Reserved Reserved Mask [7:0] Dword 1 Reserved Reserved Mask [15:8] Dword 3 Dword 0 Dword 2 Reserved Reserved Mask [23:16] Dword 5 Dword 4 Reserved Reserved Mask [31:24] Dword 7 Dword 6 ....
Programming Interface — Ethernet Controller I210 8.23.1.1 Host Slave Command I/F Flow This interface is used for the external host software to access the MMS sub-system. The host software can write a command block or read data structure directly from the DATA RAM. The host software controls these transactions through a slave access to the control register. The following flow describes the process of initiating a command to the MMS: 1. The software device driver takes ownership of the SW_FW_SYNC.
Ethernet Controller I210 — Programming Interface 8.23.3 Host Interface Buffer Base Address - HIBBA (0x8F40; RW) Notes: 1. This register is reset by a firmware reset. 2. This resister is accessible to the host driver only if Memory Base Enable is set in HICR; otherwise, the register is read only to the host driver. Field Bit(s) Initial Value Description BA 19:0 0x17800 Host interface buffer base address in the device internal memory space (in bytes). Base address for the CSR slave access.
Programming Interface — Ethernet Controller I210 8.24.1 Parity and ECC Error Indication- PEIND (0x1084; RC) Field Bit(s) Initial Value Description lanport_parity_fatal_ind (LH) 0 0b Fatal Error detected in LAN port memory. Bit is latched high and cleared on read. mng_parity_fatal_ind (RC) 1 0b Fatal Error detected in management memory. Bit is latched high and cleared on read. pcie_parity_fatal_ind (RC) 2 0b Fatal Error detected in PCIe memory. Bit is latched high and cleared on read.
Ethernet Controller I210 — Programming Interface 8.24.3 Packet Buffer ECC Status - PBECCSTS (0x245c; R/W) Field Bit(s) Init. Description ecc_en 0 0x1 ECC Enable. Reserved 1 0x0 Reserved Write 0, ignore on read. pb_cor_err_sta(R/ W1C) 2 0x0 DBU RAM correctable error indication. Bit is clean by write 1b. Reserved 31:3 0x0 Reserved. Write 0x0, ignore on read. 8.24.
Programming Interface — Ethernet Controller I210 Field Reserved Bit(s) Initial Value 2:0 0x0 Description Reserved. Write 0x0, ignore on read. Rx CDQ 0 Parity Error. PAR ERR RX CDQ 0 3 0b Indicates detection of parity error in RAM if PCIEERRCTL.ERR EN RX CDQ 0 is set. When set, stops all PCIe and DMA Rx and Tx activity from the function. To recover from this condition, the software device driver should issue a software reset by asserting CTRL.RST and re-initializing the port (refer to Section 7.6.
Ethernet Controller I210 — Programming Interface 8.24.7 PCIe ECC Status Register - PCIEECCSTS (0x5BAC; R/W1C) Field Reserved Bit(s) Initial Value 3:0 0 ECC ERR TX WR DATA 4 0b ECC ERR RETRY BUF 5 0b Reserved 31:6 0x0 8.24.8 Note: Description Reserved Tx Write Request Data ECC Correctable Error TX Retry Buffer ECC Correctable Error Reserved Write 0, ignore on read PCIe ACL0 and ACL1 Register - PCIACL01 (0x5B7C; RO to Host) Reset by PCIe reset.
Programming Interface — Ethernet Controller I210 8.24.11 LAN Port Parity Error Status Register - LANPERRSTS (0x5F58; R/ W1C) Field Reserved retx_buf Bit(s) Initial Value 8:0 0x0 9 0b Description Reserved. Write 0x0, ignore on read. retx_buf Parity Error Indication. When set to 1b, indicates detection of parity error in the RETX buffer (re-transmit buffer) RAM if LANPERRCTL.retx_buf_en is set. When set, disables packet transmission.
Ethernet Controller I210 — Programming Interface Field EXIT_DC (SC) Bit(s) Initial Value Description 25 0b Exit DMA Coalescing. Software can initiate a one time move out of the DMA coalescing state by setting this bit to 1b. OBFF_STATUS (RO) 27:26 00b OBFF Status. This field reflects the OBFF status as decoded by the PCIe: 00b = OBFF_DISABLE, OBFF is disabled. 01b = OBFF_ACTIVE, OBFF active mode - no coalescing done. 10b = OBFF_IDLE, OBFF idle mode - do not transmit anything.
Programming Interface — Ethernet Controller I210 8.25.3 DMA Coalescing Management Threshold - DMCMNGTH (0x8F30;RW) Field Reserved Bit(s) 3:0 Initial Value 0b DMCMNGTHR 19:4 0x100 Reserved 31:20 0b 8.25.4 Description Reserved. Write 0x0, ignore on read. DMA Coalescing Management Threshold. This value defines the DMA coalescing management threshold in 16 byte units.
Ethernet Controller I210 — Programming Interface 8.25.6 Flow Control Receive Threshold Coalescing - FCRTC (0x2170; R/ W) Field Reserved Bit(s) 3:0 Initial Value 0x0 Description Reserved. Write 0x0 ignore on read. Flow control receive threshold high watermark value used to generate a XOFF flow control packet when executing DMA coalescing, internal transmit FIFO is empty and transmit flow control is enabled (CTRL.TFCE = 1b).
Programming Interface — Ethernet Controller I210 8.25.9 Latency Tolerance Reporting (LTR) Minimum Values - LTRMINV (0x5BB0; R/W) Field LTRV Bit(s) 9:0 Initial Value 0x5 Description Latency Tolerance Value. This field indicates the latency tolerance supported when conditions for minimum latency tolerance exist (Refer to Section 5.11.2.1). LTRV values are multiplied by 32,768 ns or 1,024 ns depending on the Scale field, to indicate latency tolerance supported in nanoseconds.
Ethernet Controller I210 — Programming Interface 8.25.10 Latency Tolerance Reporting (LTR) Maximum Values - LTRMAXV (0x5BB4; R/W) Field LTRV Bit(s) 9:0 Initial Value 0x5 Description Latency Tolerance Value. This field indicates the latency tolerance supported when conditions for maximum latency tolerance exist (Refer to Section 5.11.2.2). LTRV values are multiplied by 32,768 ns or 1,024 ns depending on the Scale field to indicate latency tolerance supported in nanoseconds.
Programming Interface — Ethernet Controller I210 8.25.11 Latency Tolerance Reporting (LTR) Control - LTRC (0x01A0; R/ W) Field Reserved Bit(s) 0 Initial Value 0b Description Reserved. Write 0b, ignore on read. LTR Send Minimum Values. When set to 1b, the I210 sends a PCIe LTR message with the LTR snoop value, LTR no-snoop value and LTR requirement bits as defined in the LTRMINV register. LTR_MIN 1 0b Notes: 1.
Ethernet Controller I210 — Programming Interface 8.25.12 Field Energy Efficient Ethernet (EEE) Register - EEER (0x0E30; R/W) Bit(s) Initial Value Description Time expressed in microseconds that no data is transmitted following a move from the EEE TX LPI link state to a link active state. This field holds the transmit Tw_sys_tx value negotiated during EEE LLDP negotiation. Tw_system 15:0 0x0 Notes: 1. If this value is lower than the minimum Tw_sys_tx value defined in IEEE802.3az clause 78.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description 0b Force EEE Auto-negotiation. When this bit is set to 1b,it enables EEE operation in the internal MAC logic even if the link partner does not support EEE. Should be set to 1b to enable testing of EEE operation via MAC loopback (refer to y). 29 X EEE Support Negotiated on Link. 0b = EEE operation not supported on link. 1b = EEE operation supported on link.
Ethernet Controller I210 — Programming Interface Field Bit(s) Enable Automatic Crossover 1b1 0 10BASE-TE Initial Value 0b2 1 Description When set, the device automatically determines whether or not it needs to cross over between pairs so that an external cross-over cable is not required. Enable Low Amplitude 10BASE-T Operation. Setting this bit enables the I210 to operate in IEEE802.3az 10BASE-Te low power operation. 0b = 10BASE-Te operation disabled. 1b = 10BASE-Te operation enabled.
Programming Interface — Ethernet Controller I210 Field Bit(s) Initial Value Description Disable 1000 6 0b When set, disables 1000 Mb/s in all power modes. This bit is loaded from the Giga Disable bit in the Software Defined Pins Control Flash word on reset. SPD_B2B_EN 7 1b SPD Back-to-Back Enable. rst_compl (RO, LH) 8 0b Indicates PHY internal reset cleared. Disable 100 in non-D0a 9 0b Disables 100 Mb/s and 1000 Mb/s operation in non-D0a states.
Ethernet Controller I210 — Programming Interface MAC Specific Control Register 1 Page 2, Register 16 section 8.27.3.23 on page 569. MAC Specific Interrupt Enable Register Page 2, Register 18 section 8.27.3.24 on page 569. MAC Specific Status Register Page 2, Register 19 section 8.27.3.25 on page 570. Copper RX_ER Byte Capture Page 2, Register 20 section 8.27.3.26 on page 570. MAC Specific Control Register 2 Page 2, Register 21 section 8.27.3.27 on page 571.
Programming Interface — Ethernet Controller I210 12 Auto-Negotiation Enable R/W 11 Power Down R/W 10 Isolate RO 9 8 Restart Copper Auto-Negotiation Copper Duplex Mode R/W, SC R/W 0x1 0x0 0x0 0x1 Update Changes to this bit are disruptive to the normal operation. A write to this register bit does not take effect until any one of the following occurs: • Software reset is asserted (register 0_0.15). • Restart auto-negotiation is asserted (register 0_0.9). • Power down (register 0_0.
Ethernet Controller I210 — Programming Interface 7 Collision Test RO 0x0 0x0 This bit has no effect. 6 Speed Selection (MSB) R/W 0x1 Update Changes to this bit are disruptive to the normal operation;.As a result, any changes to these registers must be followed by a software reset to take effect. A write to this register bit does not take effect until any one of the following occurs: • Software reset is asserted (Register 0_0.15). • Restart Auto-Negotiation is asserted (Register 0_0.9).
Programming Interface — Ethernet Controller I210 2 Copper Link Status RO,LL 0x0 0x0 This register bit indicates when link was lost since the last read. For the current link status, either read this register back-to-back or read register 17_0.10 Link Real Time. 1b = Link is up. 0b = Link is down. 1 Jabber Detect RO,LH 0x0 0x0 1b = Jabber condition detected. 0b = Jabber condition not detected. 0 Extended Capability RO Always 1b Always 1b 1b = Extended register capabilities. 8.27.3.
Ethernet Controller I210 — Programming Interface 13 Remote Fault R/W 0x0 Update A write to this register bit does not take effect until any one of the following occurs: • Software reset is asserted (register 0_0.15). • Restart Auto-Negotiation is asserted (register 0_0.9). • Power down (register 0_0.11, 16_0.2); transitions from power down to normal operation and the copper link goes down. 1b = Set remote fault bit. 0b= Do not set remote fault bit. 12 Reserved R/W 0x0 Update Reserved.
Programming Interface — Ethernet Controller I210 10BASE-TX FullDuplex 6 R/W 5 10BASE-TX HalfDuplex R/W 4:0 Selector Field R/W 8.27.3.6 Bits 0x01 Update A write to this register bit does not take effect until any one of the following occurs: • Software reset is asserted (register 0_0.15). • Restart auto-negotiation is asserted (register 0_0.9). • Power down (register 0_0.11, 16_0.2); transitions from power down to normal operation and the copper link goes down. If register 0_0.
Ethernet Controller I210 — Programming Interface 8 100BASE-TX FullDuplex Capability RO 0x0 0x0 Received Code Word Bit 8. 1b = Link partner is 100BASE-TX full-duplex capable. 0b = Link partner is not 100BASE-TX full-duplex capable. 7 100BASE-TX HalfDuplex Capability RO 0x0 0x0 Received Code Word Bit 7. 1b = Link partner is 100BASE-TX half-duplex capable. 0b = Link partner is not 100BASE-TX half-duplex capable. 6 10BASE-T FullDuplex Capability RO 0x0 0x0 Received Code Word Bit 6.
Programming Interface — Ethernet Controller I210 8.27.3.8 Bits Copper Next Page Transmit Register - Page 0, Register 7 Field Mode HW Rst SW Rst Description 15 Next Page R/W 0x0 0x0 A write to register 7_0 implicitly sets a variable in the autonegotiation state machine indicating that the next page has been loaded. Link fail clears Reg 7_0. Transmit Code Word Bit 15. 14 Reserved RO 0x0 0x0 Reserved. 13 Message Page Mode R/W 0x1 0x1 Transmit Code Word Bit 13.
Ethernet Controller I210 — Programming Interface 8.27.3.10 Bits 15:13 12 11 10 560 1000BASE-T Control Register - Page 0, Register 9 Field Test Mode MASTER/SLAVE Manual Configuration Enable MASTER/SLAVE Configuration Value Port Type Mode R/W R/W R/W R/W HW Rst 0x0 0x0 SW Rst Description Retain TX_CLK comes from the RX_CLK pin for jitter testing in test modes 2 and 3. After exiting the test mode, hardware reset or software reset (register 0_0.
Programming Interface — Ethernet Controller I210 1000BASE-T FullDuplex 9 R/W 8 1000BASE-T HalfDuplex R/W 7:0 Reserved R/W 8.27.3.11 Bits 0x1 0x00 Update A write to this register bit does not take effect until any of the following also occurs: • Software reset is asserted (register 0_0.15). • Restart auto-negotiation is asserted (register 0_0.9). • Power down (register 0_0.11, 16_0.2); transitions from power down to normal operation and the copper link goes down. 1b = Advertise.
Ethernet Controller I210 — Programming Interface 8.27.3.12 Bits 15:14 MMD Access Control Register (MMDAC) - Page 0, Register 13 Field Function Mode R/W HW Rst 0x0 SW Rst 0x0 Description 00b 01b 10b 11b = = = = Address. Data, no post increment. Data, post increment on reads and writes. Data, post increment on writes only. 13:5 Reserved RO 0x000 0x000 Reserved. 4:0 DEVAD RO 0x00 0x00 Device Address. 8.27.3.
Programming Interface — Ethernet Controller I210 11 Downshift Enable R/W 0x0 Update Changes to these bits are disruptive to the normal operation. As a result, any changes to these registers must be followed by software reset to take effect. 1b = Enable downshift. 0b = Disable downshift. 10 Force Copper Link Good R/W 0x0 Retain If link is forced to be good, the link state machine is bypassed and the link is always up. In 1000BASE-T mode this has no effect. 1b = Force link good.
Ethernet Controller I210 — Programming Interface 8.27.3.16 Bits 15:14 Copper Specific Status Register 1 - Page 0, Register 17 Field Speed Mode RO HW Rst 0x2 SW Rst Description Retain These status bits are valid only after resolved bit 17_0.11 = 1b. The resolved bit is set when auto-negotiation completes or autonegotiation is disabled. 11b = Reserved. 10b = 1000 Mb/s. 01b = 100 Mb/s. 00b = 10 Mb/s. 13 Duplex RO 0x0 Retain This status bit is valid only after resolved bit 17_0.11 = 1b.
Programming Interface — Ethernet Controller I210 2 Reserved RO 0x0 0x0 Reserved for future use. 1 Polarity (real time) RO 0x0 0x0 1b = Reversed. 0b = Normal polarity reversal can be disabled by writing to register 16_0.1. In 1000BASE-T mode, polarity of all pairs are shown in register 21_5.3:0. 0 Jabber (real time) RO 0x0 0x0 1b = Jabber. 0b = No jabber. 8.27.3.
Ethernet Controller I210 — Programming Interface 2 Reserved R/W 0x0 Retain Reserved for future use. This bit must be 0. 1 Polarity Changed Interrupt Enable R/W 0x0 Retain 1b = Interrupt enable. 0b = Interrupt disable. 0 Jabber Interrupt Enable R/W 0x0 Retain 1b = Interrupt enable. 0b = Interrupt disable. 8.27.3.
Programming Interface — Ethernet Controller I210 8.27.3.19 Bits Copper Specific Control Register 2 - Page 0, Register 20 Field Mode HW Rst SW Rst Description 15:8 Reserved R/W 0x000 Retain Reserved. 7 10Base-Te Enable R/W 0b Retain 0b = Disable 10BASE-Te. 1b = Enable 10BASE-Te. 6 Break Link On Insufficient IPG R/W 0x0 Retain 0b = Break link on insufficient IPGs in 10BASE-T and 100BASE-TX. 1b = Do not break link on insufficient IPGs in 10BASE-T and 100BASE-TX.
Ethernet Controller I210 — Programming Interface 8.27.3.22 Bits 15 14 13 12 Copper Specific Control Register 3 - Page 0, Register 23 Field 1000BASE-T Transmitter type Disable 1000BASE-T Reverse Autoneg Disable 100BASET Mode R/W HW Rst 0 R/W R/W R/W SW Rst Description Retain 0 = Class B. 1 = Class A. Retain When set to disabled, 1000BASE-T isnot advertised even if registers 9_0.9 or 9_0.8 are set to 1b.
Programming Interface — Ethernet Controller I210 3:2 100 MB test select R/W 0x0 Retain 0xb = Normal 0peration. 10b = Select 112 ns sequence. 11b = Select 16 ns sequence. 1 10 BT polarity force R/W 0x0 Retain 1b = Force negative polarity for receive only. 0b = Normal operation. 0 Reserved R/W 0x0 Retain Reserved. 8.27.3.23 Bits MAC Specific Control Register 1 - Page 2, Register 16 Field Mode HW Rst SW Rst Retain 00b 01b 10b 11b Update Reserved. R/W Retain 1b = Stop fi_125_clk.
Ethernet Controller I210 — Programming Interface 3 FIFO Idle Inserted Interrupt Enable R/W 0x0 Retain 1b = Interrupt enable. 0b = Interrupt disable. 2 FIFO Idle Deleted Interrupt Enable R/W 0x0 Retain 1b = Interrupt enable. 0b = Interrupt disable. 1:0 Reserved R/W 0x0 Retain 0x0. 8.27.3.25 Bits MAC Specific Status Register - Page 2, Register 19 Field Mode HW Rst SW Rst Description Always 0x0 Always 0x0 Reserved.
Programming Interface — Ethernet Controller I210 8.27.3.27 Bits 15 14 MAC Specific Control Register 2 - Page 2, Register 21 Field Reserved Copper Line Loopback Mode R/W R/W HW Rst 0x0 0x0 SW Rst Description 0x0 Reserved. 0x0 1b = Enable loopback of MDI-to-MDI. 0b = Normal operation. 13:12 Reserved R/W 0x1 Update Reserved. 11:7 Reserved R/W 0x0 0x0 Reserved. 6 Reserved R/W 0x1 Update Reserved. 5:4 Reserved R/W 0x0 Retain Reserved.
Ethernet Controller I210 — Programming Interface 8.27.3.28 Bits 15:12 572 jt_led_s[3:0] Function Control Register - Page 3, Register 16 Field jt_led_s[3] Control Mode R/W HW Rst 0x1 SW Rst Retain Description If 16_3.11:10 is set to 11b then 16_3.15:12 has no effect. 0000b = On - fiber link, off - else. 0001b = On - link, blink - activity, off - no link. 0010b = On - link, blink - receive, off - no link. 0011b = On - activity, off - no activity. 0100b = Blink - activity, off - no activity.
Programming Interface — Ethernet Controller I210 11:8 7:4 3:0 jt_led_s[2] Control jt_led_s[1] Control jt_led_s[0] Control R/W R/W R/W 0x7 0x7 0x7 Retain 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b = = = = = = = = = = = = = = = = On - link, off - no link. On - link, blink - activity, off - no link. Reserved. On - activity, off - no activity. Blink - activity, off -no activity. On - transmit, off - no transmit.
Ethernet Controller I210 — Programming Interface 8.27.3.29 Bits 15:12 jt_led_s[3:0] Polarity Control Register - Page 3, Register 17 Field jt_led_s[5], jt_led_s[3], jt_led_s[1] Mix Percentage Mode R/W HW Rst 0x8 SW Rst Description Retain When using 2 terminal bi-color LEDs the mixing percentage should not be set greater than 50%. 0000b = 0%. 0001b = 12.5%, . . .. 0111b = 87.5%. 1000b = 100%. 1001b to 1111b = Reserved.
Programming Interface — Ethernet Controller I210 000b 001b 010b 011b 100b 101b = 42 ms. = 84 ms. = 170 ms. = 340 ms. = 670 ms. to 111b = Reserved. 10:8 Blink Rate R/W 0x1 Retain 7:4 Reserved R/W 0x0 Retain 0x0. Retain 00b = 84 ms. 01b= 170 ms. 10b = 340 ms. 11b = 670 ms Retain 00b 01b 10b 11b 3:2 Speed Off Pulse Period 1:0 Speed On Pulse Period 8.27.3.31 Bits R/W R/W 0x1 0x1 = = = = 84 ms. 170 ms. 340 ms. 670 ms.
Ethernet Controller I210 — Programming Interface 9:8 7:4 3:0 jt_led_s[4] Polarity jt_led_s[5] Control jt_led_s[4] Control 8.27.3.32 R/W R/W R/W 0x0 0x7 0x3 Retain 00b 01b 10b 11b = = = = On On On On Retain If 19_3.3:2 is set to 11b then 19_3.7:4 has no effect. 0000b = On - receive, off - no receive. 0001b = On - link, blink - activity, off - no link. 0010b = On - link, blink - receive, off - no link. 0011b = On - activity, off - no activity. 0100b = Blink - activity, off -no activity.
Programming Interface — Ethernet Controller I210 8.27.3.33 Bits 15:7 1000BASE-T Pair Swap and Polarity - Page 5, Register 21 Field Mode Reserved RO Register 20_5 and 21_5 Valid 6 RO HW Rst 0x0 0x0 SW Rst Description 0x0 Reserved. 0x0 The contents of 21_5.5:0 and 20_5.15:0 are valid only if Register 21_5.6 = 1b 1b = Valid. 0b = Invalid. 5 C, D Crossover RO 0x0 0x0 1b = Channel C received on MDI[2]¬± channel D received on MDI[3]¬±.
Ethernet Controller I210 — Programming Interface 8.27.3.35 Bits Copper Port CRC Counters - Page 6, Register 17 Field Mode HW Rst SW Rst Description 15:8 Packet Count RO 0x0 Retain 0x00 = no packets received. 0xFF = 256 packets received (max count). Bit 16_6.4 must be set to 1b in order for register to be valid. 7:0 CRC Error Count RO 0x0 Retain 0x00 = no CRC errors detected in the packets received. 0xFF = 256 CRC errors detected in the packets received (max count). Bit 16_6.
Programming Interface — Ethernet Controller I210 8.27.4 XMDIO Register Description Register Name Register Address Table and Page PCS Control 1 Register Device 3, register 0 section 8.27.4.1 on page 579. PCS Status 1 Register Device 3, register 1 section 8.27.4.2 on page 579. PCS EEE Capability Register Device 3, register 20 section 8.27.4.3 on page 580. PCS EEE Wake Error Counter Device 3, register 22 section 8.27.4.4 on page 580.
Ethernet Controller I210 — Programming Interface 8.27.4.3 Bits PCS EEE Capability Register - Device 3, Register 20 Field Mode HW Rst SW Rst Description 15:7 Reserved RO 0x000 Retain Reserved 6 10GBASE-KR EEE RO 0x0 Retain 1b = EEE is supported for 10GBASE-KR. 0b = EEE is not supported for 10GBASE-KR. 5 10GBASE-KX4 EEE RO 0x0 Retain 1b = EEE is supported for 10GBASE-KX4. 0b = EEE is not supported for 1000BASE-KX RO.
Programming Interface — Ethernet Controller I210 2 1000BASE-T EEE R/W 0x0 Retain 1b = EEE is supported for 1000BASE-T. 0b = EEE is not supported for 1000BASE-T. 1 100BASE-TX EEE R/W 0x0 Retain 1b = EEE is supported for 100BASE-TX. 0b = EEE is not supported for 100BASE-TX. 0 Reserved RO 0x0 Retain Reserved. 8.27.4.6 Bits EEE Link Partner Advertisement Register - Device 7, Register 61 Field Mode HW Rst SW Rst Description 15:7 Reserved RO 0x000 Retain Reserved.
Ethernet Controller I210 — Programming Interface 8.27.5.1 Bits 15 Fiber Control Register - Page 26, Register 16 Field Fiber Reset Mode R/W 14 Loopback R/W 13:12 Reserved R/W 11:10 Power Down R/W 9:0 Reserved RO 8.27.5.2 Bits 15:0 Bits 0x0 0x0 Always 0x0 SW Rst Description SC Fiber Software Reset. Affects page 1. Writing a 0x1 to this bit causes the PHY state machines to be reset. When the reset operation completes, this bit is cleared to 0x0 automatically.
Programming Interface — Ethernet Controller I210 3:2 Pattern Select R/W 00 Retain 00b 01b 10b 11b 1 PRBS Checker Enable R/W 0x0 0x0 0b = Disable. 1b = Enable. 0 PRBS Generator Enable R/W 0x0 0x0 0b = Disable. 1b = Enable. 8.27.5.4 Bits 15:0 PRBS Error Count LSB Bits 15:0 Bits 15:3 2:0 Mode RO HW Rst 0x0 SW Rst Retain Description A read to this register freezes register 25_26. Cleared only when register 23_26.4 is set to 0b.
Ethernet Controller I210 — Programming Interface 8.27.5.7 Bits Polarity Control - Page 26, Register 27 Field Mode HW Rst SW Rst Description 15 Invert rxp/n Polarity R/W Retain The latest event that occurs between the register write and pin control determines the polarity. 0b = Normal. 1b = Invert. 14 Invert txp/n Polarity R/W Retain The latest event that occurs between the register write and pin control determines the polarity. 0b = Normal. 1b = Invert.
Programming Interface — Ethernet Controller I210 8.27.5.9 Bits 15:7 6:3 2:0 Voltage Regulator Control - Page 26, Register 30 Field Reserved scr09 Output Voltage Select scr15 Output Voltage Select Mode R/W R/W R/W HW Rst 0x0 SW Rst Description Retain 0x0. Retain The latest event that occurs between the register write and pin control determines the current output amplitude setting. 0000b = 0.70V 0001b = 0.725V 0010b = 0.75V 0011b = 0.775V 0100b = 0.80V 0101b = 0.825V 0110b = 0.85V 0111b = 0.
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PCIe Programming Interface—Ethernet Controller I210 9.0 PCIe Programming Interface 9.1 PCIe* Compatibility PCIe is completely compatible with existing deployed PCI software. To achieve this, PCIe hardware implementations conform to the following requirements: • All devices required to be supported by deployed PCI software must be enumerable as part of a tree through PCI device enumeration mechanisms.
Ethernet Controller I210 —PCIe Programming Interface Table 9-1. Configuration Registers (Continued) RWS Read-write register: Register bits are read-write and can be either set or reset by software to the desired state. Bits are not cleared by reset and can only be reset with the PWRGOOD signal. Devices that consume AUX power are not allowed to reset sticky bits when AUX power consumption (either via AUX power or PME enable) is enabled.
PCIe Programming Interface—Ethernet Controller I210 Table 9-2.
Ethernet Controller I210 —PCIe Programming Interface Table 9-2. PCIe Configuration Registers Map (Continued)Byte Offset Section Byte 3 Next Capability Ptr. (0x1C0) 0x1A0 TPH Requester capability Byte 2 Byte 1 Version (0x1) Byte 0 TPH Capability ID (0x17) 0x1A4 TPH Requester Capability Register 0x1A8 TPH Requester Control Register 0x1AC: 0x1B8 TPH Steering Table Next Capability Ptr.
PCIe Programming Interface—Ethernet Controller I210 9.3.3 Command Register (0x4; R/W) This is a read/write register. Bit(s) R/W 1 Initial Value Description 0 R/W 0b I/O Access Enable 1 R/W 0b Memory Access Enable 2 R/W 0b Bus Master Enable (BME) 3 RO 0b Special Cycle Monitoring Hardwired to 0b. 4 RO 0b MWI Enable Hardwired to 0b. 5 RO 0b Palette Snoop Enable Hardwired to 0b. 6 RW 0b Parity Error Response 7 RO 0b Wait Cycle Enable Hardwired to 0b.
Ethernet Controller I210 —PCIe Programming Interface 9.3.5 Revision (0x8; RO) The default revision ID for the I210 A1 stepping is 0x01 and 0x03 for A2 stepping. The value of the rev ID is a logic XOR between the default value and the value in Flash word 0x1E. 9.3.6 Class Code (0x9; RO) The class code is a RO hard coded value that identifies the I210’s functionality. 0x020000/0x010000 - Ethernet/SCSI Adapter1 • 9.3.
PCIe Programming Interface—Ethernet Controller I210 9.3.11.1 32-bit LAN BARs Mode Mapping This mapping is selected when bit 10 in the Functions Control Flash word is equal to 1b. Table 9-4. BAR Base Address Setting in 32bit BARs Mode (BARCTRL.
Ethernet Controller I210 —PCIe Programming Interface Table 9-6. Base Address Registers' Fields Field Bits R/W Description The length of the RW bits and RO 0b bits depend on the mapping window sizes. Init value of the RW fields is 0x0. Address Space (Low register for 64bit Memory BARs) 9.3.12 31:4 R/W Mapping Window RO bits Memory CSR + FLASH BAR size depends on BARCTRL.FLBARSize and BARCTRL.CSRSize fields. 16:4 for 128KB 17:4 for 256KB and so on...
PCIe Programming Interface—Ethernet Controller I210 9.3.16 Cap_Ptr (0x34; RO) The Capabilities Pointer field (Cap_Ptr) is an 8-bit field that provides an offset in the device's PCI configuration space for the location of the first item in the Capabilities Linked List (CLL). The I210 sets this bit and implements a capabilities list to indicate that it supports PCI power management, Message Signaled Interrupts (MSIs), and PCIe extended capabilities.
Ethernet Controller I210 —PCIe Programming Interface 9.4.1.1 Capability ID (0x40; RO) This field equals 0x01 indicating the linked list item as being the PCI Power Management registers. 9.4.1.2 Next Pointer (0x41; RO) This field provides an offset to the next capability item in the capability list. In LAN function, a value of 0x50 points to the MSI capability. 9.4.1.
PCIe Programming Interface—Ethernet Controller I210 Bits 15 14:13 Default 0b (at power up) 01b R/W Description R/W1CS PME_Status This bit is set to 1b when the function detects a wake-up event independent of the state of the PME_En bit. Writing a 1b clears this bit. RO Data_Scale This field indicates the scaling factor to be used when interpreting the value of the Data register. This field equals 01b (indicating 0.
Ethernet Controller I210 —PCIe Programming Interface D0 (Consume/ Dissipate) Function D3 (Consume/ Dissipate) Common PMCSR.Data Select 0x0 / 0x4 0x3 / 0x7 0x8 Function 0 Flash addr 0x22 Flash addr 0x22 Flash addr 0x22 For other Data_Select values, the Data register output is reserved (0x0). 9.4.2 MSI Configuration This structure is required for PCIe devices.
PCIe Programming Interface—Ethernet Controller I210 Bits Default R/W Description 7 1b RO 64-bit capable A value of 1b indicates that the I210 is capable of generating 64-bit message addresses. 8 1b1 RO MSI per-vector masking. A value of 1b indicates that the I210 is capable of per-vector masking. This field is loaded from the MSI-X Configuration (Offset 0x16) Flash word. 15:9 0b RO Reserved Write 0 ignore on read. 1. Default value is read from the Flash. 9.4.2.
Ethernet Controller I210 —PCIe Programming Interface In contrast to the MSI capability structure, which directly contains all of the control/status information for the function's vectors, the MSI-X capability structure instead points to an MSI-X table structure and a MSI-X Pending Bit Array (PBA) structure, each residing in memory space. Each structure is mapped by a Base Address Register (BAR) belonging to the function, located beginning at 0x10 in configuration space.
PCIe Programming Interface—Ethernet Controller I210 Table 9-8. MSI-X Capability Structure Byte Offset Byte 3 0x70 Byte 2 Message Control (0x00090) Byte 1 Byte 0 Next Pointer (0xA0) Capability ID (0x11) 0x74 Table Offset 0x78 PBA offset 9.4.3.1 Capability ID (0x70; RO) This field equals 0x11 indicating the linked list item as being the MSI-X registers. 9.4.3.2 Next Pointer (0x71; RO) This field provides an offset to the next capability item in the capability list.
Ethernet Controller I210 —PCIe Programming Interface 9.4.3.4 Bits 31:3 2:0 MSI-X Table Offset (0x74; R/W) Default 0x000 0x3/0x4 9.4.3.5 Bits 31:3 2:0 Type Description RO Table Offset Used as an offset from the address contained by one of the function’s BARs to point to the base of the MSI-X table. The lower three table BIR bits are masked off (set to zero) by software to form a 32-bit Qword-aligned offset.
PCIe Programming Interface—Ethernet Controller I210 9.4.4.2 IODATA Register (0x9C; R/W) This is a read/write register. Register is cleared at Power-up or PCIe reset. Bit(s) R/W R/W1 31:0 Initial Value 0x0 Description Data field for reads or writes to the Internal register or internal memory location as identified by the current value in IOADDR. All 32 bits of this register are read/write-able. 1.
Ethernet Controller I210 —PCIe Programming Interface 9.4.5.4 VPD Data (0xE4; RW) This register contains the VPD read/write data. Bits 31:0 Default X 9.4.6 R/W RW Description VPD Data VPD data can be read or written through this register. The LSB of this register (at offset four in this capability structure) corresponds to the byte of VPD at the address specified by the VPD Address register. The data read from or written to this register uses the normal PCI byte transfer capabilities.
PCIe Programming Interface—Ethernet Controller I210 9.4.6.3 PCIe CAP (0xA2; RO) The PCIe capabilities register identifies the PCIe device type and associated capabilities. This is a read only register. Bits Default R/W Description 3:0 0010b RO Capability Version Indicates the PCIe capability structure version number. The I210 supports both version 1 and version 2 as loaded from the PCIe Capability Version bit in the Flash. 7:4 0000b RO Device/Port Type Indicates the type of PCIe function.
Ethernet Controller I210 —PCIe Programming Interface Bits R/W Default Description 27:26 RO 00b Slot Power Limit Scale Hardwired in the I210 to 0b, as the I210 consumes less than the 25 W allowed for its form factor. 28 RO 1b1 Function Level Reset (FLR) Capability A value of 1b indicates the function supports the optional FLR mechanism. 31:29 RO 000b Reserved 1. Loaded from Flash. 9.4.6.5 Device Control (0xA8; RW) This register controls the PCIe specific parameters.
PCIe Programming Interface—Ethernet Controller I210 Bits 11 R/W RW Default Description 1b Enable No Snoop Snoop is gated by NONSNOOP bits in the GCR register in the CSR space. 14:12 RW 010b Max Read Request Size - this field sets maximum read request size for the Device as a requester. 000b = 128 bytes 001b = 256 bytes. 010b = 512 bytes (the default value). 011b = 1 KB. 100b = Reserved. 101b = Reserved. 110b = Reserved. 111b = Reserved.
Ethernet Controller I210 —PCIe Programming Interface 9.4.6.7 Link Capabilities Register (0xAC; RO) This register identifies PCIe link specific capabilities. This is a read only register Bits 3:0 9:4 11:10 14:12 Rd/Wr RO RO RO RO Default 0010b 0x01 11b Usage depended. See default values in Section 6.2.14. Description Max Link Speed This field indicates the supported Link speed(s) of the associated link port. Defined encodings are: 0001b = 2.5 Gb/s Link speed supported.
PCIe Programming Interface—Ethernet Controller I210 Bits Rd/Wr Default Description 21 RO 0b Link Bandwidth Notification Capability Status Not supported in the I210. RO as zero. 22 RO 1b ASPM Optionality Compliance Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests. 23 RO 00b Reserved 31:24 HwInit 0x0 Port Number The PCIe port number for the given PCIe link. Field is set in the link training phase. 9.4.6.
Ethernet Controller I210 —PCIe Programming Interface Bits R/W Default Description 10 RO 0b Link Bandwidth Management Interrupt Enable Not supported in the I210. RO as zero. 11 RO 0b Link Autonomous Bandwidth Interrupt Enable Not supported in the I210. RO as zero. 15:12 RO 0000b Reserved 9.4.6.9 Link Status (0xB2; RO) This register provides information about PCIe link specific parameters. This is a read only register.
PCIe Programming Interface—Ethernet Controller I210 . Bit Location R/W Default Description Completion Timeout Ranges Supported This field indicates the I210 support for the optional completion timeout programmability mechanism. This mechanism enables system software to modify the completion timeout value. Description of the mechanism can be found in Section 3.1.3.2.
Ethernet Controller I210 —PCIe Programming Interface Bit location 3:0 R/W RW Default 0000b Description Completion Timeout Value1 In devices that support completion timeout programmability, this field enables system software to modify the completion timeout value. Encoding: • 0000b = Allowable default range: 50 s to 50 ms. It is strongly recommended that the completion timeout mechanism not expire in less than 10 ms. Actual completion timeout range supported in the I210 is 16 ms to 32 ms.
PCIe Programming Interface—Ethernet Controller I210 Bit location R/W Default Description 12:11 RO 0x0 Reserved. 14:13 RW/ RO 00b Reserved. 15 RO 0 Reserved. 1. The completion timeout value must be programmed correctly in PCIe configuration space (in Device Control 2 Register); the value must be set above the expected maximum latency for completions in the system in which the I210 is installed.
Ethernet Controller I210 —PCIe Programming Interface Bits 11 R/W Default RWS Description 0b Compliance SOS When set to 1b, the LTSSM is required to send SOS periodically in between the (modified) compliance patterns. 12 RWS 0b Compliance De-emphasis This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. Encodings: 1b -3.5 dB 0b -6 dB When the Link is operating at 2.5 GT/s, the setting of this bit has no effect.
PCIe Programming Interface—Ethernet Controller I210 Table 9-10. PCIe Extended Capability Structure Capability Next Header1 Offset Advanced Error Reporting 0x100 0x140 Serial Number 0x140 0x1A0 TLP processing hints 0x1A0 0x1C0 Latency Tolerance Requirement Reporting 0x1C0 0x000 1. Some of the capabilities might be skipped if disabled via Flash. 9.5.1 Advanced Error Reporting (AER) Capability The PCIe AER capability is an optional extended capability to support advanced error reporting.
Ethernet Controller I210 —PCIe Programming Interface Bit Location Attribute 3:0 RO 0x0 4 R/W1CS 0b Data Link Protocol Error Status RO 0b Surprise Down Error Status (Optional) Not supported in the I210.
PCIe Programming Interface—Ethernet Controller I210 Bit Location Attribute Default Value 17 RWS 0b Receiver Overflow Mask 18 RWS 0b Malformed TLP Mask 19 RWS 0b ECRC Error Mask 20 RWS 0b Unsupported Request Error Mask Description 21 RO 0b ACS Violation Mask Not supported in the I210. 22 RO 0b Uncorrectable Internal Error Mask (Optional) Not supported in the I210. 23 RO 0b MC Blocked TLP Mask (Optional) Not supported in the I210.
Ethernet Controller I210 —PCIe Programming Interface Default Value Bit Location Attribute 24 RO 0b AtomicOps Egress Blocked Severity (Optional) Not supported in the I210. 25 RO 0b TLP Prefix Blocked Error Severity (Optional) Not supported in the I210. 31:26 RO 0x0 Reserved 9.5.1.5 Description Correctable Error Status (0x110; R/W1CS) The Correctable Error Status register reports error status of individual correctable error sources on a PCIe device.
PCIe Programming Interface—Ethernet Controller I210 Bit Location Attribute 14 RO 0b Corrected Internal Error Mask (Optional) Not supported in the I210. 15 RO 0b Header Log Overflow Mask (Optional) Not supported in the I210. 31:16 RO 0x0 Reserved 9.5.1.
Ethernet Controller I210 —PCIe Programming Interface 9.5.2 Serial Number The PCIe device serial number capability is an optional extended capability that can be implemented by any PCIe device. The device serial number is a read-only 64-bit value that is unique for a given PCIe device. Note: The I210 does not support this capability in an configuration. Byte Offset 0x140 Byte 3 Byte 2 Next Capability Ptr.
PCIe Programming Interface—Ethernet Controller I210 Serial number definition in the I210: Table 9-12. SN Definition Bit(s) Location Attributes Description 63:0 RO PCIe Device Serial Number This field contains the IEEE defined 64-bit extended unique identifier (EUI-64™). This identifier includes a 24-bit company ID value assigned by IEEE registration authority and a 40-bit extension identifier assigned by the manufacturer.
Ethernet Controller I210 —PCIe Programming Interface • Serial number ADDR +7 = Flash byte 0 The official document defining EUI-64 is: http://standards.ieee.org/regauth/oui/tutorials/EUI64.html 9.5.3 TLP Processing Hint Requester (TPH) Capability The PCIe TPH Requester capability is an optional extended capability to support TLP Processing Hints. The following table lists the PCIe TPH extended capability structure for PCIe devices. Byte Offset 0x1A0 Byte 3 Byte 2 Next Capability Ptr.
PCIe Programming Interface—Ethernet Controller I210 9.5.3.2 TPH Requester Capabilities (0x1A4; RO) Default Value Bit Location Attribute 0 RO 1 No ST Mode Supported: When set indicates the Function is capable of generating Requests without using ST. 1 RO 0 Interrupt Vector Mode Supported: Cleared to indicate that the I210 does not support Interrupt Vector Mode of operation. Description 2 RO 1 Device Specific Mode: Set to indicate that the I210 supports Device Specific Mode of operation.
Ethernet Controller I210 —PCIe Programming Interface 9.5.3.4 TPH Steering Table (0x1AC - 0x1B8; R/W) Bit Location Attribute 7:0 RW Default Value Description 0x0 Steering Table Lower Entry 2*n (n = 0...3). A value of zero indicates the tag is not valid Steering Table Upper Entry 2*n (n = 0...3) - RO zero in the I210, as extended tags are not supported. 15:8 RO 0x0 23:16 RW 0x0 Steering Table Entry 2*n + 1 (n = 0...
PCIe Programming Interface—Ethernet Controller I210 9.5.4.1 LTR CAP ID (0x1C0; RO) Default Value Bit Location Attribute 15:0 RO 0x18 LTR Capability ID PCIe extended capability ID indicating LTR capability. 19:16 RO 0x1 Version Number PCIe LTR extended capability version number. 31:20 RO 0x000 Next Capability Pointer 9.5.4.
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System Manageability—Ethernet Controller I210 10.0 System Manageability Network management is an important requirement in today's networked computer environment. Software-based management applications provide the ability to administer systems while the operating system is functioning in a normal power state (not in a pre-boot state or powered-down state). The Intel® Out of Band Management fill the management void that exists when the operating system is not running or fully functional.
Ethernet Controller I210 —System Manageability The sideband interface provides a mechanism by which the I210 can be shared between the host and the MC. By providing this sideband interface, the MC can communicate with the LAN without requiring a dedicated Ethernet controller. The I210 supports two sideband interfaces: • SMBus • NC-SI • PCIe (together with MCTP) - when the system is up. The usable bandwidth for either direction is up to 1 Mb/s when using SMBus and 100 Mb/s for the NCSI interface.
System Manageability—Ethernet Controller I210 10.2 Components of the Sideband Interface There are two components to a sideband interface: • Physical Layer • Logical Layer The MC and the I210 must be in alignment for both components. An example issue: the NC-SI physical interface is based on the NC-SI interface, but there are differences between the devices at the physical level and the protocol layer is completely different. 10.2.
Ethernet Controller I210 —System Manageability Table 10-1.
System Manageability—Ethernet Controller I210 10.2.2 Logical Layer 10.2.2.1 Legacy SMBus The protocol layer for SMBus consists of commands the MC issues to configure filtering for the I210 management traffic and the reading and writing of Ethernet frames over the SMBus interface. There is no industry standard protocol for sideband traffic over SMBus. The protocol layer for SMBus on the I210 is Intel proprietary. The Legacy SMBus protocol is described in Section 10.5. 10.2.2.
Ethernet Controller I210 —System Manageability 10.3.1 Manageability Receive Filtering This section describes the manageability receive packet filtering flow. Packet reception by the I210 can generate one of the following results: • Discarded • Sent to Host memory • Sent to the external MC • Sent to both the MC and Host memory The decisions regarding forwarding of packets to the Host and to the MC are separate and are configured through two sets of registers.
System Manageability—Ethernet Controller I210 Some general rules apply: • Fragmented packets are passed to manageability but not parsed beyond the IP header. • Packets with L2 errors (CRC, alignment, etc.) are not forwarded to the MC. • Packets longer than 2KB are filtered out. The following sections describe the manageability filtering, followed by the final filtering rules. The filtering rules are created by programming the decision filters as described in Section 10.3.4. 10.3.2 L2 Filters 10.3.2.
Ethernet Controller I210 —System Manageability 10.3.3.1 ARP Filtering ARP filtering — The I210 supports filtering of ARP request packets (initiated externally) and ARP responses (to requests initiated by the MC). In legacy SMBus mode, the ARP filters can be used as part of the ARP offload described in Section 10.5.3. ARP offload is not specifically available when using NC-SI.
System Manageability—Ethernet Controller I210 10.3.3.4 ICMP Filtering The I210 supports filtering by ICMP. This filter matches if the IP protocol field equals to 1. 10.3.3.5 Flexible Port Filtering The I210 implements 16 flex destination port filters. The I210 directs packets whose L4 destination port matches to the MC. The MC must ensure that only valid entries are enabled in the decision filters. For each flex port filter, filtering can be enabled for UDP, TCP or both.
Ethernet Controller I210 —System Manageability 2. Filter Data — The filter data is divided into groups of bytes, described below: Group Test Bytes 0x0 0-29 0x1 30-59 0x2 60-89 0x3 90-119 0x4 120-127 Each group of bytes need to be configured using a separate command, where the group number is given as a parameter. The command has the following parameters: a. Group number — A 1-byte field indicating the current group addressed b.
System Manageability—Ethernet Controller I210 10.3.4.1 Manageability Decision Filters Manageability decision filters are a set of eight filters, each with the same structure. The filtering rule for each decision filter is programmed by the MC and defines which of the L2, VLAN, EtherType and L3/ L4 filters participate in decision making. Any packet that passes at least one rule is directed to manageability and possibly to the Host. With the I210, packets can also be filtered by EtherType.
Ethernet Controller I210 —System Manageability L2 EtherType 3 1.7 L2 EtherType 0 1.3 Flex TCO 1.24 Flex Port 15 1.23 Flex Port 0 1.8 Port 0x26F 0.31 Port 0x298 0.30 Neighbor Discovery (134/135/136/137) 0.29, 1.25- 1.27 ARP Request 0.27 ARP Response 0.28 Broadcast 0.25 L2 unicast address 0 0.21 L2 unicast address 3 ICMP MLD L2 EtherType 0 0.24 1.28 MANC[1] 1.29 1.0 L2 EtherType 3 1.3 IPv4 address 0 0.13 IPv4 address 3 0.16 IPv6 address 0 0.17 IPv6 address 3 0.
System Manageability—Ethernet Controller I210 A decision filter (for any of the 8 filters) defines which of the above inputs is enabled as part of a filtering rule. The MC programs two 32-bit registers per rule (MDEF[7:0] & MDEF_EXT[7:0]) with the settings as described in Section 8.22.7 and Section 8.22.8. A set bit enables its corresponding filter to participate in the filtering decision. 10.3.4.
Ethernet Controller I210 —System Manageability The MNGONLY is also configurable when using NC-SI using the Set Intel Filters — Manageability Only Command (see Section 10.6.3.5.3). All manageability filters are controlled by the MC only and not by the LAN device driver. 10.3.5 Possible Configurations This section describes ways of using management filters. Actual usage may vary. 10.3.5.1 Dedicated MAC Packet Filtering • Select one of the eight rules for dedicated MAC filtering.
System Manageability—Ethernet Controller I210 • IP Unicast filtering — requires filtering for Link Local address and a Global address. Filtering setup might depend on whether or not the MAC address is shared with the Host or dedicated to manageability: — Dedicated MAC address (for example, dynamic address allocation with DHCP does not support multiple IP addresses for one MAC address). In this case, filtering can be done at L2 using two dedicated unicast MAC filters.
Ethernet Controller I210 —System Manageability Table 10-1 Interface NC-SI (over RMII or over MCTP) Filtering Programming Interfaces Flexible/Abstract Abstract (dedicated MAC address) The regular NC-SI commands can be used to allow forwarding based on a dedicated MAC address. The list of supported commands can be found in Section 10.6.2. When using these commands, one of the two other modes can be used to add finer grain filtering.
System Manageability—Ethernet Controller I210 10.3.7.2.1 Ports Owned by the MC A small subset of the TCP and UDP ports is dedicated to the out-of-band management controller. The remaining ports are assigned to the host operating system. Hence, port-based filtering - and commands to configure it - is required. For example, port-based filtering would be used to route WSManagement packets to the out-of-band management controller.
Ethernet Controller I210 —System Manageability Aplication Networking stack Port 0 Driver NC-SI Channel N Port N Driver ... Port 0 Port N ... MC NC-SI Channel 0 MNG/host mux MNG/host mux Network Controller External Network Figure 10-2. OS-to-MC Diagram Note: This flow assumes that the MC does not share a MAC address with the Host.
System Manageability—Ethernet Controller I210 10.4.2.3 MC-to-OS Filtering When OS-to-MC is enabled, as with regular MC transmit traffic, the port (OS or network) to which the packet is sent is fixed according to the source MAC address of the packet. After that, the MC traffic will be filtered according to the L2 Host filters of the selected port (as described in Section 7.1.1). According to the results of the filtering the packet can be forwarded to the OS, the network or both.
Ethernet Controller I210 —System Manageability 10.4.3 Blocking of network to MC flow In some systems the MC may have its own private connection to the network and may use the I210 port only for the OS-to-MC traffic. In this case, the MC to network flow should be blocked while enabling the OS-to-MC and OS to network flows. This can be done by clearing the MANC.EN_BMC2NET bit for the relevant port.
System Manageability—Ethernet Controller I210 10.5 SMBus Pass-Through Interface SMBus is the system management bus defined by Intel. It is used in personal computers and servers for low-speed system management communications. This section describes how the SMBus interface operates in pass-through mode. 10.5.
Ethernet Controller I210 —System Manageability When the external MC uses the same IP and MAC address of the OS, the ARP operation should be coordinated with the Host operating system. Note: If sharing the MAC and IP with the Host operating system is possible, the I210 provides the ability to read the stem MAC address, allowing the MC to share the MAC address. There is no mechanism however provided by the I210 to read the IP address.
System Manageability—Ethernet Controller I210 Table 10-7. ARP Response Packet (Continued) Offset (Continued 28+ S + D # of bytes 4 Field Value Sender IP Address Programmed from Flash or MC 32 +S + D 6 Target HW Address ARP Request Sender HW Address 38 +S + D 4 Target IP Address ARP Request Sender IP Address 10.5.4 SMBus Transactions This section gives a brief overview of the SMBus protocol. Following is an example for a format of a typical SMBus transaction.
Ethernet Controller I210 —System Manageability 10.5.4.2 SMBus ARP Functionality The I210 supports the SMBus ARP protocol as defined in the SMBus 2.0 specification. The I210 is a persistent slave address device so its SMBus address is valid after power-up and loaded from the Flash. The I210 supports all SMBus ARP commands defined in the SMBus specification both general and directed. SMBus ARP capability can be disabled through the Flash. 10.5.4.
System Manageability—Ethernet Controller I210 Figure 10-3 shows the I210 SMBus ARP flow.
Ethernet Controller I210 —System Manageability 10.5.4.4 SMBus ARP UDID Content The UDID provides a mechanism to isolate each device for the purpose of address assignment. Each device has a unique identifier.
System Manageability—Ethernet Controller I210 Silicon Revision ID: Silicon Version Revision ID A0 000b A1 001b A2 011b Vendor Specific ID: Four LSB bytes of the device Ethernet MAC address. The device Ethernet address is taken from words LAN Base Address + Offsets 0x00-0x02 in the Flash. 1 Byte 1 Byte 1 Byte 1 Byte MAC Address, Byte 3 MAC Address, Byte 2 MAC Address, Byte 1 MAC Address, Byte 0 MSB 10.5.4.5 LSB Concurrent SMBus Transactions The SMBus interface is single threaded.
Ethernet Controller I210 —System Manageability — Power state change There can be cases where the MC is hung and not responding to the SMBus notification. The I210 has a time-out value (defined in the Flash) to avoid hanging while waiting for the notification response. If the MC does not respond until the time out expires, the notification is de-asserted and all pending data is silently discarded. Note that the SMBus notification time-out value can only be set in the Flash. The MC cannot modify this value.
System Manageability—Ethernet Controller I210 8 1 8 1 1 Data Byte Low A Data Byte High A P Interface 0 Alert Value 0 The target address and data byte low/high is taken from the Receive Enable command or Flash configuration. 10.5.5.3 Direct Receive Method If configured, the I210 has the capability to send a message it needs to transfer to the external MC as a master over the SMBus instead of alerting the MC and waiting for it to read the message. The message format follows.
Ethernet Controller I210 —System Manageability The maximum size of the received packet is limited by the I210 hardware to 1536 bytes. Packets larger then 1536 bytes are silently discarded. Any packet smaller than 1536 bytes is processed. 10.5.7 Transmit TCO Flow The I210 is used as the channel for transmitting packets from the external MC to the network link. The network packet is transferred from the MC over the SMBus and then, when fully received by the I210, is transmitted over the network link.
System Manageability—Ethernet Controller I210 10.5.7.2 TCO Command Aborted Flow The I210 indicates to the MC an error or an abort condition by setting the TCO Abort bit (See Section 10.5.9.2.2) in the general status. The I210 might also be configured to send a notification to the MC (see Section 10.5.9.1.3.3). Following is a list of possible error and abort conditions: • Any error in the SMBus protocol (NACK, SMBus timeouts, etc.).
Ethernet Controller I210 —System Manageability 1 7 1 1 8 1 8 1 1 S Slave Address Wr A Command A PEC A P 1100 001 0 0 Targeted Slave Address | 0 0 [Data Dependent Value] 0 10.5.8.4 Assign Address This command assigns SMBus address. The address and command bytes are always acknowledged. The transaction is aborted (NACKed) immediately if any of the UDID bytes is different from I210 UDID bytes. If successful, the manageability system internally updates the SMBus address.
System Manageability—Ethernet Controller I210 8 1 8 1 8 1 1 Data 16 A Data 17 A PEC A P UDID Byte 0 (LSB) 0 Assigned Address 0 [Data Dependent Value] 0 10.5.8.5 Get UDID (General and Directed) The general get UDID SMBus transaction supports a constant command value of 0x03 and, if directed, supports a Dynamic command value equal to the dynamic SMBus address.
Ethernet Controller I210 —System Manageability 8 1 8 1 8 1 8 1 Data 12 A Data 13 A Data 14 A Data 15 A UDID Byte 4 0 UDID Byte 3 0 UDID Byte 2 0 UDID Byte 1 0 8 1 8 1 Data 16 UDID Byte 0 (LSB) A Data 17 0 Device Slave Address ··· 8 1 1 A PEC ~Ã P 0 [Data Dependent Value] 1 The Get UDID command depends on whether or not this is a Directed or General command. The General Get UDID SMBus transaction supports a constant command value of 0x03.
System Manageability—Ethernet Controller I210 10.5.9.1.1 Transmit Packet Command The Transmit Packet command behavior is detailed in Section 10.5.7. The Transmit Packet fragments have the following format. The payload length is limited to the maximum payload length set in the Flash. If the overall packet length is bigger than 1536 bytes, the packet is silently discarded.
Ethernet Controller I210 —System Manageability Table 10-10. Receive Control Byte Field Bit(s) Description 0 Receive TCO Enable. 0b: Disable receive TCO packets. 1b: Enable Receive TCO packets. Setting this bit enables all manageability receive filtering operations. Enabling specific filters is done via the Flash or through special configuration commands.
System Manageability—Ethernet Controller I210 10.5.9.1.3.1 Management MAC Address (Data Bytes 7:2) Ignored if the CBDM bit is not set. This MAC address is used to configure the dedicated MAC address. In addition, it is used in the ARP response packet when the EN_ARP_RES bit is set. This MAC address is also used when CBDM bit is set in subsequent short versions of this command. 10.5.9.1.3.2 Management IP Address (Data Bytes 11:8) This IP address is used to filter ARP request packets. 10.5.9.1.3.
Ethernet Controller I210 —System Manageability Where TCO Mode is: Field Bit(s) Description 0 Perform TCO Reset. 0b: Do nothing. 1b: Perform TCO reset. 1 Do TCO Isolate 0b = Enable PCIe write access to LAN port. 1b = Isolate Host PCIe write operation to the port Note: Should be used for debug only. RESET_MGMT 2 Reset manageability; re-load manageability Flash words. 0b = Do nothing 1b = Issue firmware reset to manageability. Setting this bit generates a one-time firmware reset.
System Manageability—Ethernet Controller I210 10.5.9.1.6 Update Management Receive Filter Parameters This command is used to set the manageability receive filters parameters. The command is 0xCC. The first data byte is the parameter number and the data that follows (length and content) are parameter specific as listed in management RCV filter parameters. If the parameter that the MC sets is not supported by the I210, then the I210 does not NACK the transaction.
Ethernet Controller I210 —System Manageability Table 10-12. Management Receive Filter Parameters Parameter Flex Port Filters IPv4 Filters IPv6 Filters MAC Filters EtherType Filters Extended Decision Filter Management Special Filter Modifiers 666 Number Parameter Data 0x63 Three bytes are required to load the manageability flex port filters. Data 2: Flex port filter number. Data 3: MSB of flex port filter. Data 4: LSB of flex port filter.
System Manageability—Ethernet Controller I210 Table 10-13. Filter Enable Parameters Bit Name 16:0 Description Reserved Reserved 17 RCV_TCO_EN TCO Receive Traffic Enabled. When bit is set receive traffic to the manageability block is enabled. This bit should be set only if at least one of EN_BMC2OS or EN_BMC2NET bits are set. This bit is usually set using the receive enable command (see Section 10.5.9.1.3). 18 KEEP_PHY_LINK_UP Block PHY reset and power state changes.
Ethernet Controller I210 —System Manageability Function Set Common Filters Command 0xC2 Byte Count 29 Data 1 Data 2:4 5:10 Opcode = 0 Receive Control see Table 1014 MAC Addres s Data 11 MC Alert Address Data 12 Interface Data Byte Data 13 Alert Value Byte Data 14:29 IPv6 Address Table 10-14. Set Common Filters Receive Control Bytes Byte Bit Description 0 RCV_EN Receive TCO Packets Enabled. When this bit is set it enables the receive flow to the manageability block.
System Manageability—Ethernet Controller I210 Table 10-14. Set Common Filters Receive Control Bytes (Continued) Byte Bit 8 Description CBDM Description Configure the MC Dedicated MAC Address. 0b: The I210 shares the MAC address for MNG traffic with the host MAC address, which is specified in Flash words 0x0-0x2. 1b: The I210 uses the MC dedicated MAC address as a filter for incoming receive packets. The MC MAC address is set in bytes 5-10 in this command.
Ethernet Controller I210 —System Manageability 10.5.9.1.8 Clear all Filters Command The Clear all Filters command is a single fragment command capable of clearing all the receive filters currently programmed for manageability traffic. Function Command Clear all Filters 10.5.9.2 Byte Count 0xC3 1 Data 0x00 Read SMBus Transactions This section details the pass-through read transactions that the MC can send to the I210 over SMBus.
System Manageability—Ethernet Controller I210 The controller should retry the command later. It is recommended to wait 300 ms before retrying the command. 10.5.9.2.1 Receive TCO LAN Packet Transaction The MC uses this command to read packets received on the LAN and its status. When the I210 has a packet to deliver to the MC, it asserts the SMBus notification for the MC to read the data (or direct receive).
Ethernet Controller I210 —System Manageability The status is 8 bytes where byte 0 (bits 7:0) is set in Data 2 of the status and byte 7 in Data 9 of the status. Table 10-17 lists the content of the status data. Table 10-17. TCO LAN Packet Status Data Name Bits Description Packet Length 13:0 Packet length including CRC, only 14 LSB bits. Reserved 15:14 Reserved Packet status 31:16 See Table 10-18 VLAN 47:32 The two bytes of the VLAN header tag. MNG status 63:48 See Table 10-20.
System Manageability—Ethernet Controller I210 The I210 response to one of the commands (0xC0 or 0xD0) in a given time as defined in the SMBus Notification Timeout and Flags word in the Flash.
Ethernet Controller I210 —System Manageability Bits 2 and 1 indicate that the LAN device driver is stuck. Bit 2 indicates whether the interrupt line of the LAN function is asserted. Bit 1 indicates whether the LAN device driver dealt with the interrupt line before the last Read Status cycle. Table 10-22 lists status data byte 2. Table 10-22. Status Data Byte 2 Bit Name Description 7:5 Reserved Reserved. 4 Reserved Reserved 3 Driver Valid Indication 0b = LAN driver is not alive.
System Manageability—Ethernet Controller I210 Function Byte Count Data 1 (Op-Code) Data 2 … Data 7 Get system MAC address 7 0xD4 MAC address MSB … MAC address LSB 10.5.9.2.4 Read Management Parameters Command In order to read the management parameters the MC should execute two SMBus transactions. The first transaction is a block write that sets the parameter that the MC wants to read. The second transaction is block read that reads the parameter.
Ethernet Controller I210 —System Manageability The parameter that is returned might not be the parameter requested by the MC. The MC should verify the parameter number (default parameter to be returned is 0x1). If the parameter number is 0xFF, it means that the data that was requested from the I210 is not ready yet.The MC should retry the read transaction. It is responsibility of the MC to follow the procedure previously defined.
System Manageability—Ethernet Controller I210 Parameter # Filters Enable 0x01 Parameter Data None MNGONLY Configuration 0x0F None Flex Filter Enable Mask and Length 0x10 None Flex Filter Data 0x11 Data 2 — Group of Flex Filter’s Bytes: 0x0 = bytes 0-29 0x1 = bytes 30-59 0x2 = bytes 60-89 0x3 = bytes 90-119 0x4 = bytes 120-127 Decision Filters 0x61 This command is obsolete. Please use 0x68 instead.
Ethernet Controller I210 —System Manageability Read Receive Enable 15 (0x0F) Receive Control Byte 0xDA MAC Addr MSB MAC Addr LSB … IP Addr MSB IP Addr LSB … MC SMBus Addr I/F Data Byte Alert Value Byte The detailed description of each field is specified in the receive enable command description in Section 10.5.9.1.3. 10.5.9.2.7 Get Controller Information Command The MC uses this command to get the controller identification.
System Manageability—Ethernet Controller I210 Table 10-25. Get Controller Information data 0x0E 4 Data 4:3: PXE FW version 0x0F 4 Data 4:3: iSCSI FW version 0x10 4 Data 4:3: uEFI FW version 0xFE 2 Wrong parameter request Returned by the I210 only. This parameter is returned on read transaction, if in the previous read command the MC sets a parameter that is not supported by the I210.
Ethernet Controller I210 —System Manageability Function Get Common Filters Byte Count 30 Command 0xD3 Data 1 0 Data 2:4 5:10 Receive Control see Table 1014 MAC Addres s Data 11 MC Alert Address Data 12 Interface Data Byte Data 13 Alert Value Byte Data 14:29 IPv6 Address If case of error the following answers may be returned Function Get Common Filters Command 0xD3 Byte Count 1 Data 1 0xFF This response is by the I210, on read common filter command when the data that should have bee
System Manageability—Ethernet Controller I210 Use the Update Manageability Filter Parameters command to update Decision Filters (MDEF) (parameter 68h). This will update MDEF[0], as indicated by the 2nd parameter (0).
Ethernet Controller I210 —System Manageability 10.5.10.2 Example 2 - Dedicated MAC, Auto ARP Response and RMCP Port Filtering This example shows a common configuration; the MC has a dedicated MAC and IP address. Automatic ARP responses will be enabled as well as RMCP port filtering. By enabling Automatic ARP responses the MC is not required to send the gratuitous ARPs as it did in Example 1.
System Manageability—Ethernet Controller I210 MDEF value of 10000000: — Bit 28 [1] – ARP Requests MDEF_EXT[0] value of 0000000h: When Enabling Automatic ARP responses, the ARP requests still go into the manageability filtering system and as such need to be designated as also needing to be sent to the Host. For this reason a separate MDEF is created with only ARP request filtering enabled. Refer to the next step for more details.
Ethernet Controller I210 —System Manageability Table 10-27. Example 2 MDEF Results Manageability Decision Filter (MDEF) Filter 0 ARP Response OR Neighbor Discovery OR Port 0x298 OR X Port 0x26F OR X Flex Port 7:0 OR Flex TCO OR 10.5.10.3 1 2 3 4 5 6 7 Example 3 - Dedicated MAC and IP Address This example provided the MC with a dedicated MAC and IP address and allows it to receive ARP requests. The MC is then responsible for responding to ARP requests.
System Manageability—Ethernet Controller I210 The 2nd parameter (00h) indicates which MAC Address filter is being configured, in this case filter 0. The 3rd parameter is the MAC Address - AABBCCDD Step 5: Configure MDEF[0] for IP and MAC Filtering Update Manageability Filter Parameters [68, 0, 00002001, 000000000] Use the Update Manageability Filter Parameters command to update Decision Filters (MDEF) (parameter 68h). This will update MDEF[0], as indicated by the 2nd parameter (0).
Ethernet Controller I210 —System Manageability Table 10-28. Example 3 MDEF Results Manageability VLAN[7:0] AND IPv6 Address[3:0] AND IPv4 Address[3:0] AND L2 Exact Address[3:0] OR Broadcast OR Multicast AND ARP Request OR ARP Response OR Neighbor Discovery OR Port 0x298 OR Port 0x26F OR Flex Port 7:0 OR Flex TCO OR 10.5.10.
System Manageability—Ethernet Controller I210 note that the XSUM enable bit may differ between Ethernet Controllers, refer to product specific documentation. Step 4: Configure VLAN 0 Filter Update Manageability Filter Parameters [62, 0, 0032] Use the Update Manageability Filter Parameters command to configure VLAN filters. Parameter 62h indicates update to VLAN Filter, the 2nd parameter indicates which VLAN filter (0 in this case), the last parameter is the VLAN ID (0032h).
Ethernet Controller I210 —System Manageability Table 10-29. Example 4 MDEF Results Manageability Decision Filter (MDEF) Filter 0 Port 0x26F OR Flex Port 7:0 OR Flex TCO OR 10.6 1 2 3 4 5 6 7 NC-SI Pass Through Interface The Network Controller Sideband Interface (NC-SI) is a DMTF industry standard protocol for the sideband interface. NC-SI uses a modified version of the industry standard RMII interface for the physical layer as well as defining a new logical layer.
System Manageability—Ethernet Controller I210 Table 10-30. NC-SI Terminology Term Definition Point-to-Point Point-to-point commonly refers to the case where only two physical communication devices are interconnected via a physical communication medium. The devices might be in a master/ slave relationship, or could be peers.
Ethernet Controller I210 —System Manageability Figure 10-4 shows an example topology for a single BMC and a single NC package. In this example, the NC package has two NC channels. Management Controller (MC) NC-SI Link NC Package Package ID = 0x0 NC Channel NC Channel Internal ChannelID=0x0 Internal ChannelID=0x1 LAN0 LAN1 Figure 10-4. Single NC Package, Two NC Channels Figure 10-5 shows an example topology for a single BMC and two NC packages.
System Manageability—Ethernet Controller I210 10.6.1.3 Data Transport Since NC-SI is based upon the RMII transport layer, data is transferred in the form of Ethernet frames. NC-SI defines two types of transmitted frames: 1. Control frames: a. Configures and control the interface b. Identified by a unique EtherType in their L2 header 2. Pass-through frames: a. Actual LAN pass-through frames transferred from/to the BMC b. Identified as not being a control frame c.
Ethernet Controller I210 —System Manageability For details, refer to the NC-SI specification. 10.6.1.3.2 NC-SI Frames Receive Flow Figure 10-6 shows the flow for frames received on the NC from the BMC. NC-SI frame received from MC Process as NC-SI Control Frame EtherType == NC-SI EtherType? Yes No Send to LAN with matching configured MAC address Yes Source MAC address == previously configured MAC address? No Drop frame (belongs to a different Package) Figure 10-6.
System Manageability—Ethernet Controller I210 Table 10-31.
Ethernet Controller I210 —System Manageability Table 10-32. Optional NC-SI Features Support Feature Implement Details MAC Address Filters Yes Supports 2 mixed MAC addresses. Channel Count Yes Supports 1 channels. VLAN Filters Yes Support 8 VLAN filters. Filtering is ignoring the CFI bit and the 802.
System Manageability—Ethernet Controller I210 5. Power State Compatibility Check: If current power state does not allow for the requested link parameters, return a a General Reason Code for a failed command (0x1) and a Command Specific Reason with Set Link Power Mode Conflict Reason (0x0904). 6.
Ethernet Controller I210 —System Manageability — Flex 128 filter — Flex TCP/UDP port filters 0x0...0xA — IPv4/IPv6 filters • Get System MAC Address — This command enables the MC to retrieve the system MAC address used by the NC. This MAC address can be used for a shared MAC address mode. • Keep PHY Link Up (Veto bit) Enable/Disable — This feature enables the MC to block PHY reset, which might cause session loss. • TCO Reset — Enables the MC to reset the I210.
System Manageability—Ethernet Controller I210 10.6.3.2 Intel OEM Commands Summary Table 10-33. Intel OEM Specific Command Response and Reason Codes Response Code Value 0x1 Description Command Failed Reason Code Value Description 0x5081 Invalid Intel Command Number 0x5082 Invalid Intel Command Parameter Number 0x5087 Invalid Driver State 0x5088 Invalid Flash 0x508D Returned when one of the shared IP commands is received with an out of range resource (IP, port, binding) index.
Ethernet Controller I210 —System Manageability Table 10-34.
System Manageability—Ethernet Controller I210 10.6.3.3 Set Intel Filters Control — IP Filters Control Command (Intel Command 0x00, Filter Control Index 0x00) This command controls different aspects of the Intel filters. Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...23 0x00 24...25 IP Filters Control (1-0) 0x00 IP Filters control (3-2) Where “IP Filters Control” has the following format. Table 10-35.
Ethernet Controller I210 —System Manageability 00...15 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...21 0x01 10.6.3.4.2 0x00 Get Intel Filters Control — IP Filters Control Response (Intel Command 0x01, Filter Control Index 0x00) Bits Bytes 31:24 23:16 15:08 00...15 07:00 NC-SI Header 16...19 Response Code Reason Code 20...23 Manufacturer ID (Intel 0x157) 24...27 0x01 28...29 IP Filters Control (1-0) 0x00 IP Filters Control (3-2) IP Filter Control: See Table 10-35. 10.
System Manageability—Ethernet Controller I210 Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...23 0x02 24...25 Manageability Only (1-0) 10.6.3.5.4 0x0F Manageability Only (3-2) Set Intel Filters — Manageability Only Response (Intel Command 0x02, Filter Parameter 0x0F) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Manufacturer ID (Intel 0x157) 24...25 0x02 10.6.3.5.
Ethernet Controller I210 —System Manageability 10.6.3.5.7 Set Intel Filters — Flex Filter Data Command (Intel Command 0x02, Filter Parameter 0x11) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20... 0x02 0x11 ... Filter Data N Filter Data Group Filter Data 1 The Filter Data Group parameter defines which bytes of the Flex filter are set by this command: Table 10-36.
System Manageability—Ethernet Controller I210 10.6.3.5.10 Set Intel Filters — Flex TCP/UDP Port Filter Command (Intel Command 0x02, Filter Parameter 0x63) Bits Bytes 31:24 23:16 00...15 15:08 07:00 Port filter index TCP/UDP Port MSB NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...23 0x02 24 TCP/UDP Port LSB 0x63 Port flags Filter index range: 0x0...0xA.
Ethernet Controller I210 —System Manageability IPv4 Mode: Filter index range: 0x0...0x3. IPv6 Mode: This command should not be used in IPv6 mode. 10.6.3.5.13 Set Intel Filters — IPv4 Filter Response (Intel Command 0x02, Filter Parameter 0x64) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Manufacturer ID (Intel 0x157) Reason Code 24...25 0x02 0x64 10.6.3.5.
System Manageability—Ethernet Controller I210 If the IP filter index is larger the 3, a command failed Response Code will be returned, with Invalid Intel Parameter Number reason (0x5082). 10.6.3.5.16 Set Intel Filters - EtherType Filter Command (Intel Command 0x02, Filter parameter 0x67) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...23 0x02 0x67 EtherType Filter Index 24...27 ... ...
Ethernet Controller I210 —System Manageability Bits Bytes 31:24 23:16 15:08 07:00 Extended Decision filter MSB 20...23 0x02 0x68 Extended Decision filter Index 24...27 ... ... Extended Decision filter LSB 28...30 ... ... Extended Decision filter LSB Decision filter MSB Extended Decision filter Index Range: 0...4 Decision Filter: See Table 10-37. Extended Decision filter: See Table 10-38. Table 10-37.
System Manageability—Ethernet Controller I210 Table 10-38.
Ethernet Controller I210 —System Manageability 10.6.3.5.21 Set Intel Filters - Special Modifier Response (Intel Command 0x02, Filter parameter 0x69) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Reason Code Manufacturer ID (Intel 0x157) 24...25 0x02 0x69 10.6.3.6 Get Intel Filters Formats 10.6.3.6.1 Get Intel Filters Command (Intel Command 0x03) Bits Bytes 31:24 23:16 00...15 15:08 07:00 15:08 07:00 NC-SI Header 16...
System Manageability—Ethernet Controller I210 The MNGONLY register structure is described in Table 10-5. Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Manufacturer ID (Intel 0x157) 24...27 0x03 28...29 Manageability Only(1-0) 10.6.3.6.
Ethernet Controller I210 —System Manageability 00...15 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...22 0x03 Filter Data Group 0...4 0x11 The Filter Data Group parameter defines which bytes of the Flex filter are returned by this command: Table 10-39. Filter Data Group Code Bytes Returned 0x0 bytes 0-29 0x1 bytes 30-59 0x2 bytes 60-89 0x3 bytes 90-119 0x4 bytes 120-127 10.6.3.6.
System Manageability—Ethernet Controller I210 Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Manufacturer ID (Intel 0x157) Reason Code 24...27 0x03 28...29 TCP/UDP Port (0) 0x63 TCP/UDP Filter Index TCP/UDP Port (1) Port flags If the TCP/UDP Filter Index is bigger than 0xA, a command failed Response Code is returned with Invalid Intel Parameter Number reason (0x5082).
Ethernet Controller I210 —System Manageability 20...23 Manufacturer ID (Intel 0x157) 24...27 0x03 28...29 IPv4 Address (2-0) 0x64 IPv4 Filter Index IPv4 Address (3) 10.6.3.6.14 Get Intel Filters — IPv6 Filter Command (Intel Command 0x03, Filter Parameter 0x65) Bits Bytes 31:24 23:16 00...15 07:00 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...
System Manageability—Ethernet Controller I210 Bits Bytes 31:24 23:16 15:08 00...15 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...22 0x03 07:00 EtherType Filter Index 0x67 Valid indices: 0...3 10.6.3.6.17 Get Intel Filters - EtherType Filter Response (Intel Command 0x03, Filter parameter 0x67) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Reason Code Manufacturer ID (Intel 0x157) 24...27 0x03 0x67 EtherType Filter Index 28...
Ethernet Controller I210 —System Manageability Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Reason Code Manufacturer ID (Intel 0x157) 24...27 0x03 0x68 Decision Filter Index Extended Decision Filter MSB 28...31 .. .. Extended Decision Filter LSB Decision Filter MSB 32...34 .. .. Decision Filter LSB Where Decision Filter & Extended Decision Filter have the structure as detailed in the respective “Set” commands.
System Manageability—Ethernet Controller I210 10.6.3.7 Note: Set Intel Packet Reduction Filters Formats The non extended commands (Section 10.6.3.7.3 to Section 10.6.3.7.5) are not supported anymore. Use the extended commands (Section 10.6.3.7.6 to Section 10.6.3.7.11) instead. 10.6.3.7.1 Set Intel Packet Reduction Filters Command (Intel Command 0x04) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...23 0x04 10.6.3.7.
Ethernet Controller I210 —System Manageability Table 10-41. Extended Packet Reduction Field Description Bit # Name Description 24 Flex TCO (OR) If set, packets can pass if match the Flex 128 TCO filter 27:25 Reserved 28 ICMP If set, ICMP packets can pass 29 MLD If set, MLD packets can pass 31:30 Reserved Reserved.
System Manageability—Ethernet Controller I210 20..23 0x04 0x10 Extended Unicast Reduction Filter MSB .. 24..27 .. Extended Unicast Reduction Filter LSB Unicast Reduction Filter MSB .. 28..29 .. Unicast Reduction Filter LSB This command causes the NC to filter packets that have passed due to the unicast filter (MAC address filters, as specified in the DMTF NC-SI). Note that unicast filtering might be affected by other filters, as specified in the DMTF NC-SI.
Ethernet Controller I210 —System Manageability Note: See Table 10-40 and Table 10-41 for description of the Multicast Extended Packet Reduction format. This command causes the NC to filter packets that have passed due to the multicast filter (MAC address filters, as specified in the DMTF NC-SI). The filtering of these packets are done such that the MC might add a logical condition that a packet must match, or it must be discarded.
System Manageability—Ethernet Controller I210 Note: Packets that might have been blocked can still pass due to other decision filters. In order to disable broadcast packet reduction, the MC should set all reduction filters to 0b. Following such a setting, the NC must forward, to the MC, all packets that have passed the broadcast filters as specified in the DMTF NC-SI. The command shall overwrite any previously stored value. 10.6.3.7.
Ethernet Controller I210 —System Manageability Note: See Table 10-40 and Table 10-41 for description of the Return Data format. 10.6.3.8.3 Get Unicast Packet Reduction Command (Intel Command 0x05, Reduction Filter Index 0x00) This command is not supported anymore. Use the Get Unicast Extended Packet Reduction Command (Intel Command 0x05, Reduction Filter Index 0x10) instead (Section 10.6.3.8.6). 10.6.3.8.
System Manageability—Ethernet Controller I210 Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...21 0x05 10.6.3.8.9 0x11 Get Multicast Extended Packet Reduction Response (Intel Command 0x05, Reduction Filter Index 0x11) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Manufacturer ID (Intel 0x157) Reason Code 24...27 0x05 28...
Ethernet Controller I210 —System Manageability 10.6.3.9 System MAC Address 10.6.3.9.1 Get System MAC Address Command (Intel Command 0x06) In order to support a system configuration that requires the NC to hold the MAC address for the MC (such as shared MAC address mode), the following command is provided to enable the MC to query the NC for a valid MAC address. The NC must return the system MAC addresses.
System Manageability—Ethernet Controller I210 Where Intel Management Control 1 is as follows: Bit # Default value Description 0 0b Enable Critical Session Mode (Keep PHY Link Up and Veto Bit) 0b — Disabled 1b — Enabled When critical session mode is enabled, the following behaviors are disabled: • The PHY is not reset on PE_RST# and PCIe resets (in-band and link drop). Other reset events are not affected — Internal_Power_On_Reset, device disable, Force TCO, and PHY reset by software.
Ethernet Controller I210 —System Manageability Bits Bytes 31:24 23:16 16...19 Response Code 20...23 Manufacturer ID (Intel 0x157) 24...26 0x21 10.6.3.12 15:08 07:00 Reason Code 0x00 Intel Management Control 1 TCO Reset Depending on the bit set in the TCO mode field this command will cause the I210 to perform either: 1. TCO Reset, if Force TCO reset is enabled in the Flash (see Section 6.7.1).
System Manageability—Ethernet Controller I210 Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20 0x22 TCO Mode Where TCO Mode is: Field DO_TCO_RST Bit(s) Description Perform TCO Reset. 0b: Do nothing. 1b: Perform TCO reset. 0 DO_TCO_ISOLATE1 1 Do TCO Isolate 0b = Enable PCIe write access to LAN port. 1b = Isolate Host PCIe write operation to the port Note: Should be used for debug only.
Ethernet Controller I210 —System Manageability Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20 0x23 10.6.3.13.2 Enable Checksum Offloading Response (Intel Command 0x23) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Manufacturer ID (Intel 0x157) 24...26 0x23 Reason Code 10.6.3.13.3 Disable Checksum Offloading Command (Intel Command 0x24) Bits Bytes 31:24 23:16 00...
System Manageability—Ethernet Controller I210 10.6.3.14.1 Set IP Address Command (Intel Command 0x25, Index = 0x0) The Set IP Address command is used by the Management Controller to communicate its IP address to a Network Controller. The format of a Set IP Address command packet is specified in Table 10-42 If at least one IP address filter is enabled, only unicast packets that match one of the enabled filters will be forwarded through the NC-SI interface.
Ethernet Controller I210 —System Manageability • Table 10-44 describes the bits fields in the Set IP Flags field. Table 10-44. Set IP Flag Field Bit Position Field Description Value Description 0 Enable 0 = Disable the filter 1 = Enable the filter 1 IP version 0 = IPv4 1 = IPv6 2 Mixed index 0 = Index relates to the IPv4 or IPv6 only IP filter sets according to the IP version field. 1 = Index relates to the mixed IP filter set.
System Manageability—Ethernet Controller I210 • IP address number. Defines the index of the IP address in the pool defined by the IP filter pool. The allowed values are as defined in Table 10-43. • IP filter pool: — 0x0: Mixed IP filters — 0x1: IPv4 filters — 0x2: IPv6 filters — 0x3 - 0xFF: Reserved 10.6.3.14.2.
Ethernet Controller I210 —System Manageability Table 10-48. Get IP Flag Field Mixed Index 0 = Index relates to the IPv4 or IPv6 only IP filter sets according to the IP version field. 1 = Index relates to the mixed IP filter set. 3 MAC based IP This flags define if the Ipv6 address is derived from a MAC address and thus only the 24 LSB should be used for the comparison. This flag is relevant only if the IP version = IPv6.
System Manageability—Ethernet Controller I210 10.6.3.14.3.1Set Port Response The Network Controller shall, in the absence of a checksum error or identifier mismatch, always accept the Set Port command and send a response, using the format specified in Table 10-51. Table 10-51. Set Port Response Packet Format Bits Bytes 31..24 23..16 12..15 15..08 07..00 NC-SI Header 16..19 Response Code 20..23 Reason Code Manufacturer ID (Intel 0x157) 24..27 0x25 0x2 Reserved 28..31 Checksum 10.6.3.14.
Ethernet Controller I210 —System Manageability Table 10-54. Get Port Response Packet Format 16..19 Response Code 20..23 Reason Code Manufacturer ID (Intel 0x157) 24..27 0x25 0x3 28..31 Port Index Protocol 32..35 Get Port Flags Reserved Port Checksum • Protocol: The value compared in the IPv4 header Protocol field or IPv6 header Next Header field. Possible values are 0x6 (TCP) and 0x11 (UDP). This field is relevant only if the Ignore Protocol flag is cleared.
System Manageability—Ethernet Controller I210 The format of an Enable Unicast Infrastructure Filter command packet is specified in Table 10-56. Table 10-56. Enable Unicast Infrastructure Filter Command Bits Bytes 31..24 23..16 00..15 16..19 Response Code 20..23 24..27 15..08 07..00 NC-SI Header Reason Code Manufacturer ID (Intel 0x157) 0x25 0x4 Reserved 28..31 Unicast Infrastructure Filter Settings 32..35 Checksum 36..
Ethernet Controller I210 —System Manageability Table 10-57.
System Manageability—Ethernet Controller I210 Table 10-57.
Ethernet Controller I210 —System Manageability A Management Controller uses the Get Shared IP Capabilities command to determine the level of support of shared IP of the device. The format of a Get Shared IP Capabilities command packet is specified in Table 10-59. Table 10-59. Get Shared IP Capabilities Command Packet Format Bits Bytes 31..24 23..16 15..08 00..15 NC-SI Header 16..19 Manufacturer ID (Intel 0x157) 20..23 0x25 0x5 24..27 07..00 Reserved Checksum 10.6.3.14.6.
System Manageability—Ethernet Controller I210 • Table 10-61 describes the bits fields in the Filtering Capabilities field. Table 10-61.
Ethernet Controller I210 —System Manageability The content of the Shared IP Broadcast Packet Filter Settings field is specified in Table 10-63. Bit 4 has been added to the standard Enable Broadcast Filtering Command Limit ARP Broadcast Packets to Management Controller IP Address. Table 10-63. Shared IP Broadcast Packet Filter Settings Field Bit Position Field Description Value Description As defined in DSP0222 As defined in DSP0222 in 8.4.
System Manageability—Ethernet Controller I210 The format of an Shared IP Enable Global Multicast Filtering command packet is specified in Table 1065. Table 10-65. Shared IP Enable Global Multicast Filtering Command Bits Bytes 31..24 23..16 15..08 00..15 NC-SI Header 16..19 Manufacturer ID (Intel 0x157) 20..23 0x25 07..00 0x7 Reserved 24..27 Shared IP Multicast Packet Filter Settings 28..31 Checksum 32..
Ethernet Controller I210 —System Manageability 10.6.3.14.9 Get Shared IP Parameters Command (Intel Command 0x25, Index = 0x8) The Get Shared IP parameters command can be used by the Management Controller to request that the channel send the Management Controller a copy of part of the currently stored parameter settings that have been put into effect by the Management Controller related to shared IP filtering. The format of a Get Shared IP Capabilities command packet is specified in Table 10-68.
System Manageability—Ethernet Controller I210 Table 10-70. IP address flags Field 2 IP address 3 status or Reserved 0b = Default or unsupported or disabled 1b = Enabled IP address 24 status or Reserved 0b = Default or unsupported or disabled 1b = Enabled ...
Ethernet Controller I210 —System Manageability The Set Binding command is used by the Management Controller to define which combination of MAC addresses, VLAN tags, IP addresses and TCP/UDP ports should be forwarded to the MC. The format of a Set Binding command packet is specified in Table 10-72. Once a Set Binding command is activated, all the previous forwarding rules based on the Set MAC Address or Set VLAN filter commands are disabled and should be re-enabled using the Set Binding command.
System Manageability—Ethernet Controller I210 address can be added to a binding only if previously enabled through a Set MAC Address NC-SI command • Enabled VLAN: The VLAN IDs participating in this binding. The numbering of the VLAN IDs. A VLAN tag can be added to a binding only if previously enabled through a Set VLAN Filter NC-SI command. • Enabled IP addresses: The IP addresses participating in this binding.
Ethernet Controller I210 —System Manageability 10.6.3.14.11.1Get Binding Response The Network Controller shall, in the absence of a checksum error or identifier mismatch, always accept the Get Binding command and send a response, using the format specified in Table 10-76. Table 10-76. Get Binding Response Packet Format Bits Bytes 31..24 23..16 00..15 15..08 07..00 NC-SI Header 16..19 Response Code 20..23 Reason Code Manufacturer ID (Intel 0x157) 24..27 0x25 0xA 28..
System Manageability—Ethernet Controller I210 — 0x0: Dedictated MAC mode — 0x1: Shared MAC/IP mode. 10.6.3.14.12.1Set Shared Mode Response The Network Controller shall, in the absence of a checksum error or identifier mismatch, always accept the Set Shared Mode command and send a response, using the format specified in Table 10-78. Table 10-78. Set Shared Mode Response Packet Format Bits Bytes 31..24 23..16 00..15 15..08 NC-SI Header 16..19 Response Code 20..
Ethernet Controller I210 —System Manageability Bits Bytes 31:24 23:16 15:08 00...15 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20...21 0x40 07:00 0x02 10.6.3.15.4 Enable Network to MC Flow Response (Intel Command 0x40, Index 0x2) Bits Bytes 31:24 23:16 00...15 16...19 Response Code 20...23 24...25 15:08 07:00 NC-SI Header Reason Code Manufacturer ID (Intel 0x157) 0x40 0x02 10.6.3.15.
System Manageability—Ethernet Controller I210 Bits Bytes 31:24 23:16 15:08 00...15 NC-SI Header 16...19 Manufacturer ID (Intel 0x157) 20 07:00 0x41 10.6.3.15.8 Get OS2BMC parameters Response (Intel Command 0x41) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Reason Code Manufacturer ID (Intel 0x157) 24...27 0x41 Status Where the Status byte partition is as follow: Table 10-79.
Ethernet Controller I210 —System Manageability 10.6.3.16.1 Get Controller Information Response (Intel Command 0x48, Index 0x1) Bits Bytes 31:24 23:16 00...15 15:08 07:00 NC-SI Header 16...19 Response Code 20...23 Reason Code Manufacturer ID (Intel 0x157) 24...27 0x48 0x01 Reserved 28...31 Controller Info Item 1ID Controller Info Item 1 length ... Number of Inventory entries Controller Info Item 1 Data .... ...
System Manageability—Ethernet Controller I210 The BMC must select no more than one NC package at any given time. Package selection can be accomplished in one of two methods: 1. Select Package command — This command explicitly selects the NC package. 2. Any other command targeted to a channel in the package also implicitly selects that NC package. Package de-select can be accomplished only by issuing the De-Select Package command.
Ethernet Controller I210 —System Manageability 10.6.4.4.1 NC Capabilities Advertisement NC-SI defines the Get Capabilities command. It is recommended that the BMC use this command and verify that the capabilities match its requirements before performing any configurations. For example, the BMC should verify that the NC supports a specific AEN before enabling it. 10.6.4.4.2 Receive Filtering In order to receive traffic, the BMC must configure the NC with receive filtering rules.
System Manageability—Ethernet Controller I210 10.6.4.4.3 VLAN NC-SI defines the following VLAN work modes: Mode Command and Name Descriptions Disabled Disable VLAN command In this mode, no VLAN frames are received. Enabled #1 Enable VLAN command with VLAN only In this mode, only packets that matched a VLAN filter are forwarded to the BMC. Enabled #2 Enable VLAN command with VLAN only + non-VLAN In this mode, packets from mode 1 + non-VLAN packets are forwarded.
Ethernet Controller I210 —System Manageability The NC filters pass-through packets according to their source MAC address. The NC tries to match that source MAC address to one of the MAC addresses configured by the Set MAC Address command. As a result, the BMC should enable network transmit only after configuring the MAC address. It is recommended that the BMC complete all filtering configuration (especially MAC addresses) before enabling the network transmit.
System Manageability—Ethernet Controller I210 10.6.8 Advanced Workflows 10.6.8.1 Multi-NC Arbitration As described in Section 10.6.1.2, in a multi-NC environment, there is a need to arbitrate the NC-SI lines. Figure 10-7 shows the system topology of such an environment. MC NC-SI TX lines NC-SI RX lines NC Package1 Channel1: 0x0 Channel2: 0x1 NC Package2 Channel1: 0x0 HW-Arbitration lines Figure 10-7. Multi-NC Environment See Figure 10-7. The NC-SI Rx lines are shared between the NCs.
Ethernet Controller I210 —System Manageability 10.6.8.2 Package Selection Sequence Example Following is an example work flow for a BMC and occurs after the discovery, initialization, and configuration. Assuming the BMC needs to share the NC-SI bus between packages, the BMC should: 1. Define a time-slot for each device. 2. Discover, initialize, and configure all the NC packages and channels. 3. Issue a De-Select Package command to all the channels. 4.
System Manageability—Ethernet Controller I210 b. Check if a different channel is available (link is up). c. If found: • Enable network TX for that specific channel. • Issue a gratuitous ARP (or any other packet with its source MAC address) to the network. This packet informs the switch that this specific MAC address is registered to channel 0's specific LAN port. • Resume normal workflow. • If not found, report the error and continue polling until a valid channel is found.
Ethernet Controller I210 —System Manageability • It is recommended that the MC first query the link status using the Get Link Status command. The MC should then use this data as a basis and change only the needed parameters when issuing the Set Link command. For details, refer to the NC-SI specification. 10.6.9.
System Manageability—Ethernet Controller I210 The NC-SI over MCTP spec defines two types of MCTP message types: NC-SI (0x2) and Ethernet (0x3). The I210 supports both messages. When used only for control, then only the NC-SI (0x2) message type is supported. In addition to the above message types supported by the I210, the PCIe based VDM message type is also supported over PCIe to support ACL commands. 10.7.1.
Ethernet Controller I210 —System Manageability Both endpoints (SMBus and PCIe) may be active concurrently. However, pass through traffic may be transferred only through one of them. If the PCIe endpoint is active, it will be used for pass through traffic, otherwise, the SMBus endpoint will be used. Section 10.7.2.2 describes the transition between the two busses. For each channel (SMBus or PCIe), the I210 should expect MCTP commands from two sources: the bus owner and the MC.
System Manageability—Ethernet Controller I210 address of the MC are extracted from the Clear Initial State command parameters or any other NC-SI command received later with a channel ID of the I210. Subsequent pass through traffic will be received from or sent to this address only. If the EID or the physical address of the NIC changes, it indicates the changes to bus owner so that the routing tables can be updated. There is no attempt to directly send an indication to the MC about the change.
Ethernet Controller I210 —System Manageability Reset Reset Reset PCIe BME is cleared / Stop PT Init St at PC e M Ie ac hi ne St S at M e B M us ac hi ne Init SMBus ARP / Get SMB Addr SMBus Address in NVM PCIe BME is cleared PCIe BME is set /Send “Discovery Notify” On PCIe Undiscovered SMB “Set End Point ID” / Capture Bus owner EID Enable NC-SI over SMBus reception Discovered SMB PCIe BME is cleared Any NC-SI over SMBus Command / Capture SMBus BMC EID Active PT = SMBus Un-discovered PCI-E “S
System Manageability—Ethernet Controller I210 • After the NC-SI channels are enabled, traffic may be sent using the MC and NIC addresses previously discovered. • The MC may send a Get UUID command to get a unique identifier of the NIC that may be used later for reconnection upon topology changes. 10.7.2.2.
Ethernet Controller I210 —System Manageability • The NIC will then wait for the MC to discover it on the SMBus. The MC then discover the NIC as described in the SMBus to PCIe transition above. • The transition of NC-SI traffic (pass through or commands/responses) from PCIe to SMBus may done at any stage and may interrupt a packet fragmentation or reassembly, as it is assumed that such a transition occurs only when the PCIe bus is not available anymore.
System Manageability—Ethernet Controller I210 10.7.3.2 PCIe Discovery Process The I210 follows the discovery process described in section 5.9 of the MCTP PCIe VDM Transport Binding Specification (DSP0238). Upon reception of an Endpoint Discovery message (while in undiscovered stage), the I210 will expose the endpoint on the function previously described.
Ethernet Controller I210 —System Manageability 10.7.
System Manageability—Ethernet Controller I210 10.7.5 NC-SI Over MCTP The I211 support for NC-SI over MCTP is similar to the support for NC-SI over RMII with the following exceptions: 1. A set of new NC-SI commands used to expose the NC-SI over MCTP capabilities. 2. The format of the packets is modified to account for the new transport layer as described below. 10.7.5.1 NC-SI Packets Format NC-SI over MCTP defines two different message type for pass through and for control packets.
Ethernet Controller I210 —System Manageability Note that the MAC header and MAC FCS present when working over NC-SI are not part of the packet in MCTP mode. 10.7.5.1.2 Pass Through Packets The format used for Pass through packets is as follow. This format is the same for either packets received from the network or packets received from the host. The CRC is never included in the packet. In receive, the CRC is checked and removed by the I210 in transmit, the CRC is added by the I210.
System Manageability—Ethernet Controller I210 10.7.6.1 MCTP Commands Support Table 10-81 lists the MCTP commands supported by I211. Table 10-81. MCTP commands support Command Code 0x00 Command Name General Description I211 support as Initiator I211 support as Responder Reserved Reserved – – 0x01 Set Endpoint ID Assigns an EID to the endpoint at the given physical address. N/A Yes 0x02 Get Endpoint ID Returns the EID presently assigned to an endpoint.
Ethernet Controller I210 —System Manageability The Get Endpoint ID response of I211 is described in the following table: Byte Description Value 1 Completion Code 2 Endpoint ID 0x00 - EID not yet assigned Otherwise - returns EID assigned using Set Endpoint ID command 3 Endpoint Type 0x00 (Dynamic EID, Simple Endpoint) 4 Medium Specific SMBUs: 0x01 - Fairness arbitration protocol supported. PCIe: 0x00 10.7.6.1.
System Manageability—Ethernet Controller I210 Byte Description Value 0x02 (NC-SI over MCTP) 3:5 List of Message Type numbers 0x03 (Ethernet). If pass through is supported. 0x7E (PCIe based VDM messages) - over PCIe only 10.7.6.1.
Ethernet Controller I210 —System Manageability 10.8.2 Host Slave Command Interface to Manageability This interface is used by the software device driver for several of the commands and for delivering various types of data in both directions (Manageability-to-Host and Host-to-Manageability). The address space is separated into two areas: • Direct access to the internal data RAM: The internal shared (between Firmware and Software) RAM is mapped to address space 0x8800 to 0x8EFF.
System Manageability—Ethernet Controller I210 10.8.2.3 Host Interface Structure 10.8.2.3.1 Host Interface Command Structure Table 10-82 describes the structure used by the Software device driver to send a command to Firmware using the Host slave command interface (shared RAM mapped to addresses 0x8800-0x8EFF). Table 10-82. Host Driver Command Structure #Byte 0 Description Command Bit 7:0 Description Command Dependent Specifies which host command to process.
Ethernet Controller I210 —System Manageability 10.8.2.4 Host Interface Commands 10.8.2.4.1 Driver Info Host Command This command is used to provide the driver information in NC-SI mode. Table 10-84. Driver Info Host Command Byte Name Bit Command 1 Buffer Length 7:0 0x5 Port Number + 4 bytes of the Driver info 2 Reserved 7:0 0x0 Reserved 3 Checksum 7:0 4 Port Number 7:0 Driver Version 7:0 0xDD Description 0 8:5 7:0 Value Driver info command.
System Manageability—Ethernet Controller I210 a. Set ARP Proxy Table Entry Response (See Table 10-91). b. Set NS (Neighbor Solicitation) Proxy Table Entry Response (See Table 10-93) 10.8.2.4.2.1 Get Firmware Proxying Capabilities This command is used to provide the driver information on protocol offload types supported by the I210. Table 10-86.
Ethernet Controller I210 —System Manageability Table 10-87.
System Manageability—Ethernet Controller I210 Table 10-88. Set Firmware Proxying Configuration Command Byte Name Bit Value 0 Command 7:0 0xEB 1 Buffer length 7:0 0x6 2 Reserved 7:0 0x0 3 Checksum 7:0 4 Port Number 7:0 Description Set Firmware Proxying Configuration Must be zeroed by host Checksum signature Port Number Indicates the port number that the command is targeted at.
Ethernet Controller I210 —System Manageability Table 10-89. Set Firmware Proxying Configuration Response Byte Name Bit Value 0 Command 7:0 0xEB 1 Buffer length 7:0 0x6 Get Firmware Proxying Capabilities 0x0 0x1 0x2 0x3 0x4 0x5 - Undefined Error - Status OK - Unsupported command - Checksum Error - Buffer Length Error to 0xFF - Error 2 Return Status 7:0 3 Checksum 7:0 4 Port Number 7:0 Port Number Indicates the port number that the status is from.
System Manageability—Ethernet Controller I210 Table 10-90. Set ARP Proxy Table Entry Command Byte Name Bit Value 0 Command 7:0 0x77 1 Buffer length 7:0 0x13 2 Reserved 7:0 0x0 3 Checksum 7:0 4 Port Number 7:0 Port Number 5 Sub command 7:0 0x3 6 ARP proxy version 1 7:0 0x1 Description Set ARP proxy command Must be zeroed by host Checksum signature Indicates the port number that the command is targeted at.
Ethernet Controller I210 —System Manageability Table 10-91. Set ARP Proxy Table Entry Response Byte Name Bit Value 0 Command 7:0 0x77 1 Buffer length 7:0 0x13 0x1 Description Set ARP proxy command 0x0 0x1 0x2 0x3 0x4 0x5 0x6 - Unsupported Table Index - Status OK - Table Index in use. - Unsupported command - Checksum Error - Buffer Length Error to 0xFF - Error 2 Status 7:0 3 Checksum 7:0 4 Port Number 7:0 Port Number Indicates the port number that the response is for.
System Manageability—Ethernet Controller I210 Table 10-92. Set NS Proxy Table Entry Command Byte Name Bit Value 0 Command 7:0 0x78 1 Buffer length 7:0 0x4B 2 Reserved 7:0 0x0 3 Checksum 7:0 4 Port Number 7:0 Port Number 5 Sub command 7:0 0x3 6 NS proxy version 1 7:0 0x2 Description Set NS proxy command Must be zeroed by host Checksum signature Indicates the port number that the command is targeted at.
Ethernet Controller I210 —System Manageability Table 10-93. Set NS Proxy Table Entry Response Byte Name Bit Value 0 Command 7:0 0x78 1 Buffer length 7:0 0x4B 0x1 Description Set NS proxy command 0x0 0x1 0x2 0x3 0x4 0x5 0x6 - Unsupported Table Index - Status OK - Table Index in use. - Unsupported command - Checksum Error - Buffer Length Error to 0xFF - Error 2 Status 7:0 3 Checksum 7:0 4 Port Number 7:0 Port Number Indicates the port number that the status is for.
System Manageability—Ethernet Controller I210 Table 10-94.
Ethernet Controller I210 —System Manageability If TCO isolate is enabled in the Flash (See Section 6.7.1.3), The TCO Isolate command will disable PCIe write operations to the LAN port. As the driver needs to access the CSR space in order to provide descriptors to the NIC, this operation will also stop the network traffic including OS2BMC and MC-to-OS traffic as soon as the existing transmit and receive descriptor queues are exhausted.
Electrical/Mechanical Specification—Ethernet Controller I210 11.0 Electrical/Mechanical Specification 11.1 Introduction These specifications are subject to change without notice. This chapter describes the I210 DC and AC (timing) electrical characteristics. This includes absolute maximum rating, recommended operating conditions, power sequencing requirements, DC and AC timing specifications. The DC and AC characteristics include generic digital 3.
Ethernet Controller I210 —Electrical/Mechanical Specification 11.2.1 Symbol Recommended Operating Conditions I210 (Commercial Temperature SKU) Parameter Min Ta Operating Temperature Range (Ambient; 0 CFS airflow) 0 I210 (Industrial Temperature SKU) Max 70 Min -40 Units Notes Max 85 C 1 2 3 , , 1. For normal device operation, adhere to the limits in this table.
Electrical/Mechanical Specification—Ethernet Controller I210 11.3 Power Delivery 11.3.1 Power Supply Specification VCC3P3 (3.3V) Parameters Parameter Description Min Max Units Rise Time Time from 10% to 90% mark 0.1 50 mS Monotonicity Voltage dip allowed in ramp N/A 0 mV Slope Ramp rate at any given time between 10% and 90% Min: 0.8*V(min)/Rise time (max) Max: 0.8*V(max)/Rise time (min) 24 2880 V/S Operational Range Voltage range for normal operating conditions 2.97 3.
Ethernet Controller I210 —Electrical/Mechanical Specification Parameter Description Min Max Units Overshoot Duration Maximum overshoot allowed duration. (At that time delta voltage should be lower than 5mv from steady state voltage) 0.0 0.05 mS Decoupling Capacitance Capacitance range 15 Capacitance ESR Equivalent series resistance of output capacitance μF 50 MΩ 1. Power supply voltage with ripple should not be below minimum power supply operating range. 11.3.1.
Electrical/Mechanical Specification—Ethernet Controller I210 Aux power stable VCCP (3.3V) VCC1p5 (1.5V) VCC/VCC0p9(0.9V) T3_15 Tlpgw INTERNAL_POWER _ON_RESET Typ 6.5 ms; Max 7.5 ms T3_09 Tlpg Main Power stable Main power stable PE_RST_N Tm-per Tper-m Tlpg-per Figure 11-1. Power and Reset Sequencing 11.3.1.2 Power-On Reset Thresholds The I210 internal power-on reset circuitry initiates a full chip reset when voltage levels of power supplies reach certain thresholds at power-up. Table 11-3.
Ethernet Controller I210 —Electrical/Mechanical Specification 11.5 Current Consumption Condition D0a - active link Speed (Mb/s) Condition Total Power Internal SVR (mW) 0.9V CurrentExternal (mA) 1.5V CurrentExternal (mA) 3.3V CurrentExternal (mA) Total Power Ext. Regulator (mW) 10 Typ 381 48.3 16.3 85.1 348 100 Typ 373 54.4 24.9 75.5 334 1000 copper Typ 612 99.7 52.6 111.2 535 1000 fiber Typ 363 57.9 37.1 61.
Electrical/Mechanical Specification—Ethernet Controller I210 11.6 DC/AC Specification 11.6.1 DC Specifications 11.6.1.1 Digital I/O Table 11-4. Digital IO DC Electrical Characteristics Symbol Parameter Conditions Min Max Units Note VCC3P3 Periphery Supply 2.97 3.465 V 3.3V + 5%/3.3V -10% VCC Core Supply 0.855 0.945 V 0.9V +/- 5% VOH Output High Voltage V 3 4, 5 VOL Output Low Voltage IOH = -8 mA; VCC3P3 = Min 2.4 IOH = -100 A; VCC3P3 = Min VCC3P30.
Ethernet Controller I210 —Electrical/Mechanical Specification 11.6.1.2 LEDs I/O Table 11-5. LED IO DC Electrical Characteristics Symbol VCC3P3 Parameter Conditions Min Periphery Supply VCC Core Supply VOH Output High Voltage IOH = -20 mA; VCC3P3 = Min VOL Output Low Voltage IOL = 20 mA; VCC=Min Max 2.97 3.465 0.855 0.945 Units Note V V 2.4 V 0.45 V VCC3P3 + 0.4 V 1 V 1 VIH Input High Voltage 0.7 x VCC3P3 VIL Input Low Voltage -0.4 0.
Electrical/Mechanical Specification—Ethernet Controller I210 Table 11-7. NC-SI Pads DC Specifications (Continued) Symbol Parameter Conditions VOH2 Output High Voltage IOH = -4 mA; VCC3P3 = Min VOL Output Low Voltage IOL = 4 mA; VCC3P3 = Min VIH Input High Voltage VIL Input Low Voltage Vihyst Input Hysteresis Iil/Iih Input Current Cin Input Capacitance 1. 2. Min Max VCC3P3 0.4 V 0.4 0.7 x VCC3P3 V V 0.3 x VCC3P3 100 VCC3P3 = Max; Vin =3.
Ethernet Controller I210 —Electrical/Mechanical Specification Table 11-8. SMBus Timing Parameters (Master Mode) (Continued) Symbol Parameter Min Typ 100 Khz Typ 400 Khz Typ 1 MHz Max Units TTIMEOUT Detect SMB_CLK Low Timeout 35 35 35 35 35 ms TLOW SMB_CLK Low Time 0.5 4.7 1.3 0.5 µs THIGH SMB_CLK High Time 0.26 4 0.6 0.26 µs Table 11-9 lists the timing requirements of the I210 when it is the receiver of the indicated signal. Table 11-9.
Electrical/Mechanical Specification—Ethernet Controller I210 11.6.2.3 I2C AC Specification Table 11-10 lists the timing of the I2C_CLK and I2C_DATA pins when operating in I2C mode. Table 11-10. I2C Timing Parameters Symbol Parameter Min Typ Max Units FSCL I2C_CLK Frequency TBUF Time between Stop and Start condition driven by the I210 100 kHz 4.7 µs THD:STA Hold Time After Start Condition. After this period, the first clock is generated. 4 µs TSU:STA Start Condition Setup Time 4.
Ethernet Controller I210 —Electrical/Mechanical Specification Table 11-11. Flash I/F Timing Parameters Symbol Parameter Pad Name Min Typ Max Units Note fSCK Serial Clock (SCK) frequency for all instructions NVM_SK 3.125 MHz After power on. fSCK Serial Clock (SCK) frequency for all instructions (word 0x11 loaded) NVM_SK 12.5 MHz Dependent on the value of the Flash Speed field. fSCK Serial Clock (SCK) frequency for all instructions (LAN PLL operational) NVM_SK 62.
Electrical/Mechanical Specification—Ethernet Controller I210 Figure 11-4. Flash Timing Diagram 11.6.2.5 NC-SI AC Specification The I210 is designed to support the standard DMTF NC-SI interface. For NC-SI I/F timing specification see Table 11-12 and Figure 11-5. Table 11-12.
Ethernet Controller I210 —Electrical/Mechanical Specification gray = signals changing SIGNALS 90% Vm GND 10% Tco NC_SI_CLK_IN 90% Tsu Thd Vckm GND 10% Tck Figure 11-5. NC-SI Timing Diagram 11.6.2.6 JTAG AC Specification The I210 is designed to support the IEEE 1149.1 standard. Following timing specifications are applicable over recommended operating range from Ta = 0 oC to +70 oC, VCC3P3 = 3.3V, Cload = 16 pF (unless otherwise noted).
Electrical/Mechanical Specification—Ethernet Controller I210 Tjclk Tjsu T jh JT C K JT M S JT D I JT D O T jpr Figure 11-6. JTAG AC Timing Diagram 11.6.2.7 MDIO AC Specification The I210 is designed to support the MDIO specifications defined in IEEE 802.3 clause 22. Following timing specifications are applicable over recommended operating range from Ta = 0 oC to +70 oC (-40 oC to +85 oC for industrial temperature SKUs), VCC3P3 = 3.3V, Cload = 16 pF (unless otherwise noted).
Ethernet Controller I210 —Electrical/Mechanical Specification Tmclk Tmsu Tmh Figure 11-7. MDIO Input AC Timing Diagram Tmclk Tmpr MDC MDIO Figure 11-8. MDIO Output AC Timing Diagram 11.6.2.8 SFP 2 Wires I/F AC Specification According to Atmel's AT24C01A/02/04 definition of the 2 wires I/F bus.
Electrical/Mechanical Specification—Ethernet Controller I210 11.6.2.9 PCIe Interface DC/AC Specification The I210 PCIe Gen 1 interface supports the electrical specifications defined in: • PCI Express* 2.0 Card Electro-Mechanical (CEM) Specification. • PCI Express* 2.1 Base Specification, Chapter 4. 11.6.2.9.1 PCIe Specification - Input Clock The input clock for PCIe must be a differential input clock in frequency of 100 MHz. For full specifications please check the PCI Express* 2.
Ethernet Controller I210 —Electrical/Mechanical Specification Table 11-15. Specification for External Crystal (Continued) Parameter Name Symbol Recommended Value Topr 0 to +70 [°C] -40 to +85 [°C] Non Operating Temperature Range Topr -30 to +85 [°C] Equivalent Series Resistance (ESR) Rs 50 [] maximum Shunt Capacitance Co 6 [pF] maximum Load Capacitance Cload 16 to 18 pF Max Drive Level DL 0.
Electrical/Mechanical Specification—Ethernet Controller I210 Table 11-17. Specification for External Clock Oscillator (Continued) Frequency Tolerance Operating Temperature Maximum jitter 12KHz-20 MHz RMS f/fo ±50 [ppm] -20 to +70 [°C] Topr 0 to +70 [°C] -40 to +85 [°C] Commercial grade Industrial grade 1 1.5 [ps] 1. At the XTAL1 input. 11.6.6 Switching Voltage Regulator (SVR) Capacitor Electrical Specifications The following table lists the electrical performance of the 0.9V/1.5V SVR.
Ethernet Controller I210 —Electrical/Mechanical Specification 11.8.1 Flash Parts Type: SPI Flash Supported Flash Parts Winbond* Compatible:1 W25X40BVSNIG W25X80BVSNIG W25Q40BVSNIG W25Q80BVSNIG W25Q16 W25Q32 Winbond Validated:2 W25Q80BVSSIG. W25Q16CVSSIG. W25X16A. Micron* (Numonyx*) Compatible:1 M25PE40 M25PE80 M25PX80 N25Q032 Micron (Numonyx) Validated:2 M25PX80VMW6G. M25PE80VMW6TG. N25Q032A13ESE40F. Macronix* Compatible:1 MX25L4005 MX25L8005 MX25L1633E. MX25L1633EM2I.
Electrical/Mechanical Specification—Ethernet Controller I210 Supported Flash Parts Fidelix* Validated:2 FM25S16A AMIC* Validated:2 A25L040M Spansion* Validated:2 S25FL008K0XMF ESMT* Validated:2 F25L04PA 1. Compatible by design but not tested. 2. Validated Flash parts.
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Design Considerations—Ethernet Controller I210 12.0 Design Considerations This section provides general design considerations and recommendations when selecting components and connecting special pins to the I210.
Ethernet Controller I210 —Design Considerations 12.1.3 Other PCIe Signals The I210 also implements other signals required by the PCIe specification. The I210 signals power management events to the system using the PE_WAKE_N signal, which operates very similarly to the familiar PCI PME# signal. Finally, there is a PE_RST_N signal, which serves as the familiar reset function for the I210. 12.1.4 PCIe Routing Contact your Intel representative for information regarding the PCIe signal routing. 12.
Design Considerations—Ethernet Controller I210 12.2.2.2 Fixed Crystal Oscillator A packaged fixed crystal oscillator comprises an inverter, a quartz crystal, and passive components conveniently packaged together. The device renders a strong, consistent square wave output. Oscillators used with microprocessors are supplied in many configurations and tolerances. Crystal oscillators should be restricted to use in special situations, such as shared clocking among devices or multiple controllers.
Ethernet Controller I210 —Design Considerations 12.3 Crystal Support 12.3.1 Crystal Selection Parameters All crystals used with Intel Ethernet controllers are described as AT-cut, which refers to the angle at which the unit is sliced with respect to the long axis of the quartz stone. Table 12-19 lists crystals which have been used successfully in other designs (however, no particular product is recommended): Table 12-19. Crystal Manufacturers and Part Numbers Manufacturer Part No.
Design Considerations—Ethernet Controller I210 Note: Crystals also carry other specifications for storage temperature, shock resistance, and reflow solder conditions. Crystal vendors should be consulted early in the design cycle to discuss the application and its environmental requirements. 12.3.1.5 Crystal Oscillation Mode The terms series-resonant and parallel-resonant are often used to describe crystal oscillator circuits.
Ethernet Controller I210 —Design Considerations Note: Intel recommends COG or NPO capacitors with a tolerance of ±5% (approximately ±1 pF) or smaller. 12.3.1.7 Shunt Capacitance The shunt capacitance parameter is relatively unimportant compared to load capacitance. Shunt capacitance represents the effect of the crystal’s mechanical holder and contacts. The shunt capacitance should equal a maximum of 6 pF. 12.3.1.
Design Considerations—Ethernet Controller I210 appropriate capacitive load). A crystal with zero or near zero ppm deviation will be a good reference crystal to use in subsequent frequency tests to determine the best values for C1 and C2. • If a crystal analyzer is not available, then the selection of a reference crystal can be done by measuring a statistically valid sample population of crystals, which has units from multiple lots and approved vendors.
Ethernet Controller I210 —Design Considerations • The two load capacitors, crystal component, the Ethernet controller device, and the crystal circuit traces must all be located on the same side of the circuit board (maximum of one via-to-ground load capacitor on each XTAL trace). • Use 27 pF (5% tolerance) 0402 load capacitors. • Place load capacitor solder pad directly in line with circuit trace (see Figure 12-10, point A). • Use 50 impedance single-ended microstrip traces for the crystal circuit.
Design Considerations—Ethernet Controller I210 Note: The power consumption of additional circuitry equals about 1.5 mW. Table 12-20 lists oscillators that can be used with the I210. Please note that no particular oscillator is recommended): Table 12-20. Oscillator Manufacturers and Part Numbers Manufacturer Part No. NDK AMERICA INC 2560TKA-25M TXC CORPORATION - USA 6N25000160 or 7W25000025 CITIZEN AMERICA CORP CSX750FJB25.000M-UT Raltron Electronics Corp CO4305-25.
Ethernet Controller I210 —Design Considerations 12.5 Ethernet Interface 12.5.1 Magnetics for 1000 BASE-T Magnetics for the I210 can be either integrated or discrete. The magnetics module has a critical effect on overall IEEE and emissions conformance. The device should meet the performance required for a design with reasonable margin to allow for manufacturing variation.
Design Considerations—Ethernet Controller I210 12.5.4 Discrete/Integrated Magnetics Specifications Open Circuit Inductance (OCL) or OCL (alternate) Insertion Loss For 60 seconds 2250 Vdc (min) With 8 mA DC bias at 25 C 400 H (min) With 8 mA DC bias at 0 C to 70 C 350 H (min) 100 KHz through 999 kHz 1.0 MHz through 60 MHz 60.1 MHz through 80 MHz 80.1 MHz through 100 MHz 100.1 MHz through 125 MHz 1 dB (max) 0.6 dB (max) 0.8 dB (max) 1.0 dB (max) 2.4 dB (max) 1.0 MHz through 40 MHz 40.
Ethernet Controller I210 —Design Considerations 12.5.5 Designing the I210 as a 10/100 Mb/s Only Device To connect the I210 as a 10/100 Mb/s only device: 1. Set bit 4 of the Software Defined Pins Control (LAN Base Address + Word 0x20) to 0b. Setting bit 4 to 1b disables 1000 Mb/s (GbE) operation in all power modes (see Section 6.2.21). 2. Connect MDI pair 0 (pins 57 and 58) and MDI pair 1 (pins 54 and 55) to your magnetics.
Design Considerations—Ethernet Controller I210 M D I_ P L U S (0 ) M D I_ M IN U S (0 ) M D I_ P L U S (1 ) M D I_ M IN U S (1 ) 58 57 55 54 L A N _ 1 .5 V 1 0/1 0 0 M a g n e tics M o d u le w ith C o m m on M o d e C h o k e in B o th R x a nd T x P a th s I2 1 0 50 O hm R e sisto rs M D I_ P L U S (2 ) M D I_ M IN U S (2 ) M D I_ P L U S (3 ) M D I_ M IN U S (3 ) 53 52 50 49 Figure 12-12.I210 10/100 Mb/s Magnetics Module Connections (With CMC) 12.5.
Ethernet Controller I210 —Design Considerations Minimizing the amount of space needed for the Ethernet LAN interface is important because other interfaces compete for physical space on a motherboard near the connector. The Ethernet LAN circuits need to be as close as possible to the connector. Keep silicon traces at least 1" from edge of PB (2" is preferred). Integrated RJ-45 w/LAN Magnetics Keep LAN silicon 1" - 4" from LAN connector.
Design Considerations—Ethernet Controller I210 Magnetics Module I211 RJ-45 Integrated Connector Module I210 Figure 12-14.
Ethernet Controller I210 —Design Considerations 12.5.6.3 Board Stack-Up Recommendations Printed circuit boards for these designs typically have four, six, eight, or more layers. Although, the I210 does not dictate the stack up, here is an example of a typical six-layer board stack up: • Layer 1 is a signal layer. It can contain the differential analog pairs from the Ethernet device to the magnetics module. • Layer 2 is a signal ground layer.
Design Considerations—Ethernet Controller I210 12.5.6.4 Differential Pair Trace Routing for 10/100/1000 Designs Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through power and ground planes.
Ethernet Controller I210 —Design Considerations 12.5.6.5 Maximum Trace Lengths Based on Trace Geometry Table 12-21. Maximum Trace Lengths Based on Trace Geometry and Board Stack-Up Dielectric Thickness (mils) Dielectric Constant (DK) at 1 MHz Width / Space/ Width (mils) Pair-to-Pair Space (mils) Nominal Impedance (Ω) Impedance Tolerance (±%) Maximum Trace Length (inches)1 2.7 4.05 4/10/4 19 952 172 3.5 2.7 4.05 4/10/4 19 952 152 4 2.7 4.05 4/10/4 19 95 10 5 3.3 4.1 4.2/9/4.
Design Considerations—Ethernet Controller I210 Figure 12-16.MDI Trace Geometry 12.5.6.6 Signal Termination and Coupling The I210 has internal termination on the MDI signals. External resistors are not needed. Adding pads for external resistors can degrade signal integrity. 12.5.6.7 Signal Trace Geometry for 1000 BASE-T Designs The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to trace-height above the reference plane.
Ethernet Controller I210 —Design Considerations 12.5.6.8 Trace Length and Symmetry for 1000 BASE-T Designs As indicated earlier, the overall length of differential pairs should be less than four inches measured from the Ethernet device to the magnetics. The differential traces (within each pair) should be equal in total length to within 50 mils (1.25 mm) and as symmetrical as possible. Asymmetrical and unequal length traces in the differential pairs contribute to common mode noise.
Design Considerations—Ethernet Controller I210 • Physically group together all components associated with one clock trace to reduce trace length and radiation. • Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals. • Avoid routing high-speed LAN traces near other high-frequency signals associated with a video controller, cache controller, processor, or other similar devices. 12.5.6.
Ethernet Controller I210 —Design Considerations 1. Lack of symmetry between the two traces within a differential pair. Asymmetry can create commonmode noise and distort the waveforms. For each component and/or via that one trace encounters, the other trace should encounter the same component or a via at the same distance from the Ethernet silicon. 2. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and will distort the transmit or receive waveforms. 3.
Design Considerations—Ethernet Controller I210 8. Incorrect differential trace impedances. It is important to have ~100 impedance between the two traces within a differential pair. This becomes even more important as the differential traces become longer. To calculate differential impedance, many impedance calculators only multiply the single-ended impedance by two. This does not take into account edge-to-edge capacitive coupling between the two traces.
Ethernet Controller I210 —Design Considerations 50 MHz 3.3V 50 MHz Reference Clock Buffer 10kΩ 10kΩ 10kΩ 10kΩ 33Ω DMTF Compliant MC Device 33Ω REF_CLK NC-SI_CLK_IN CRS_DV NC-SI_CRS_DV RXD_0 NC-SI_RXD_0 RXD_1 NC-SI_RXD_1 NC-SI_TX_EN TX_EN I210 NC-SI Interface Signals 22Ω NC-SI_TXD_0 TXD_0 22Ω NC-SI_TXD_1 TXD_1 10kΩ 10kΩ 10kΩ Figure 12-17.
Design Considerations—Ethernet Controller I210 50 MHz 3.3V 50 MHz Reference Clock Buffer 10kΩ 10kΩ 10kΩ I210 NC-SI Interface Signals 10kΩ DMTF Compliant MC Device 33Ω 33Ω NC-SI_CLK_IN REF_CLK NC-SI_CRS_DV CRS_DV RXD_0 NC-SI_RXD_0 RXD_1 NC-SI_RXD_1 NC-SI_TX_EN TX_EN 22Ω NC-SI_TXD_0 TXD_0 22Ω NC-SI_TXD_1 TXD_1 10kΩ 10kΩ 10kΩ 33Ω NC-SI_CLK_IN NC-SI_CRS_DV NC-SI_RXD_0 NC-SI_RXD_1 NC-SI_TX_EN I210 NC-SI Interface Signals NC-SI_TXD_0 NC-SI_TXD_1 Figure 12-18.
Ethernet Controller I210 —Design Considerations Figure 12-19.NC-SI Connection Requirements - Hardware Arbitration 12.6.1.3 Resets It is important to ensure that the resets for the MC and I210 are generated within a specific time interval. The important requirement here is ensuring that the NC-SI link is established within two seconds of the MC receiving the power good signal from the platform.
Design Considerations—Ethernet Controller I210 8 inches NC-SI_CLK_IN NC-SI_TXD(1:0) I210 External MC NC-SI_TX_EN NC-SI_RXD(1:0) NC-SI_CRS_DV Figure 12-20.NC-SI Trace Length Requirement for Direct Connect For multi-drop applications (Figure 12-21) the spacing recommendation is a maximum of four inches. This keeps the overall length between the MC and I210 within the specification. 8 inches . I210 . NC-SI_CLK_IN NC-SI_TXD(1:0) NC-SI_TX_EN . NC-SI_RXD(1:0) NC-SI_CRS_DV . External MC .
Ethernet Controller I210 —Design Considerations 12.7 I210 Power Supplies The I210 requires three power rails: 3.3 Vdc, 1.5 Vdc, and 0.9 Vdc. Intel recommends that board designers use the integrated switching voltage regulators derived from a single 3.3 Vdc supply to reduce Bill of Material (BOM) costs. A central power supply can provide the required voltage sources designed by a system power engineer. If the LAN wake capability is used, all voltages must remain present during system power down.
Design Considerations—Ethernet Controller I210 Note: Use multiple vias to connect output to sub layer shape to feed VDD input. I210 47 VDD1p5 VDD1p5_OUT 39 15 uF 11, 32 42, 59 VDD0p9 Note: One decoupling capacitor per VDD pin (distributed) VDD0p9_OUT 38 15 uF V3p3_LAN CTOP 10, 27, 41, 64 40 0.039 uF VDD3p3 CBOT 15 uF E_PAD_GND 37 Keep close to I210. Use short wide traces. 65 Connect to ground plane using mulitple vias OPTION A: Fully Integrated 0.09 Vdc and 1.
Ethernet Controller I210 —Design Considerations 12.7.2 Ethernet Controller I210 Power Sequencing Designs must comply with power sequencing requirements to avoid latch-up and forward-biased internal diodes (see Figure 12-23). The general guideline for sequencing is: 1. Power up the 3.3 Vdc rail. 2. Power up the 1.5 Vdc next. 3. Power up the 0.9 Vdc rail last. For power down, there is no requirement (only charge that remains is stored in the decoupling capacitors). VDD3p3 VDD1p5 VDD0p9 Figure 12-23.
Design Considerations—Ethernet Controller I210 VDD3p3 VDD1p5 VDD0p9 Figure 12-24.External Voltage Regulator Power-up Sequence 12.7.2.2 Power Up-Sequence (Internal SVR) The I210 controls the power-up sequence internally and automatically with the following conditions (see Figure 12-25): • 3.3 Vdc must be the source for the internal LVR. • 1.5 Vdc never exceeds 3.3 Vdc. • 0.9 Vdc never exceeds 3.3 Vdc or 1.5 Vdc. The ramp is delayed internally, with Tdelay depending on the rising slope of the 3.
Ethernet Controller I210 —Design Considerations 12.7.3 Power and Ground Planes Good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly reduce EMI radiation. The following guidelines help reduce circuit inductance in both backplanes and motherboards: • Route traces over a continuous plane with no interruptions. Do not route over a split power or ground plane.
Design Considerations—Ethernet Controller I210 Note: 12.8.1 The DEV_OFF_N pin should maintain its state during system reset and system sleep states. It should also insure the proper default value on system power up. For example, a designer could use a GPIO pin that defaults to 1b (enable) and is on system suspend power. For example, it maintains the state in S0-S5 ACPI states).
Ethernet Controller I210 —Design Considerations 12.9 Assembly Process Flow Figure 12-26 shows the typical process flow for mounting packages to the PCB. Figure 12-26.Assembly Flow 12.10 Reflow Guidelines The typical reflow profile consists of four sections. In the preheat section, the PCB assembly should be preheated at the rate of 1 to 2 °C/sec to start the solvent evaporation and to avoid thermal shock.
Design Considerations—Ethernet Controller I210 Figure 12-27.Typical Profile Band Note: 1. Preheat: 125 °C -220 °C, 150 - 210 s at 0.4 k/s to 1.0 k/s 2. Time at T > 220 °C: 60 - 90 s 3. Peak Temperature: 245-250 °C 4. Peak time: 10 - 30 s 5. Cooling rate: <= 6 k/s 6.
Ethernet Controller I210 —Design Considerations 12.11 XOR Testing A common board or system-level manufacturing test for proper electrical continuity between the I210 and the board is some type of cascaded-XOR or NAND tree test. The I210 implements an XOR tree spanning most I/O signals. The component XOR tree consists of a series of cascaded XOR logic gates, each stage feeding in the electrical value from a unique pin.
Design Considerations—Ethernet Controller I210 dl(JTAG_TDI); dh(JTAG_TCK); dl(JTAG_TCK); dh(JTAG_TDI); dh(JTAG_TCK); dl(JTAG_TCK); dl(JTAG_TDI); dh(JTAG_TCK); dl(JTAG_TCK); dh(JTAG_TDI); dh(JTAG_TCK); dl(JTAG_TCK); dl(JTAG_TDI); dh(JTAG_TCK); dl(JTAG_TCK); dh(JTAG_TDI) dh(JTAG_TMS); dh(JTAG_TCK); dl(JTAG_TCK); dl(JTAG_TMS); dh(JTAG_TCK); dl(JTAG_TCK); dh(JTAG_TMS); dh(JTAG_TCK); dl(JTAG_TCK); dh(JTAG_TCK); dl(JTAG_TCK); dl(JTAG_TMS); dh(JTAG_TCK); dl(JTAG_TCK); hold(JTAG_TMS,JTAG_TCK,JTAG_TDI); Note: XOR
Ethernet Controller I210 —Design Considerations Table 12-23.
Thermal Considerations—Ethernet Controller I210 13.0 Thermal Considerations This section helps design a thermal solution for systems implementing the I210. It details the maximum allowable operating junction and case temperatures and provides the methodology necessary to measure these values. It also outlines the results of thermal simulations of the I210 in a standard JEDEC test environment with a 2s2p board using various thermal solutions. 13.
Ethernet Controller I210 —Thermal Considerations 13.3 Thermal Management Importance The objective of thermal management is to ensure that all system component temperatures are maintained within their functional limits. The functional temperature limit is the range in which the electrical circuits are expected to meet specified performance requirements. Operation outside the functional limit can degrade system performance, cause logic errors, or cause device and/or system damage.
Thermal Considerations—Ethernet Controller I210 13.5 Package Thermal/Mechanical Specifications and Limit 13.5.1 Thermal Limits - Max Junction/Case To ensure proper operation of the I210, the thermal solution must dissipate the heat generated by the component and maintain a case temperature at or below the values listed in Table 13-24. The I211 is designed to operate properly as long as the Tcase rating is not exceeded. Section 13.7.1 discusses proper guidelines for measuring the case temperature.
Ethernet Controller I210 —Thermal Considerations 13.5.3 Simulation Setup A simulation environment conforming to the JEDEC JESD51-2 standard was developed using a 101.5 mm x 114.5 mm, 2s2p board according to JEDEC JESD 51-9.
Thermal Considerations—Ethernet Controller I210 13.7 Component Measurement Methodology Measurement methodologies for determining the case and junction temperature are outlined in the sections that follow. 13.7.1 Case Temperature Measurements Special care is required when measuring the Tcase temperature to ensure an accurate temperature measurement is produced. Use the following guidelines when measuring Tcase: • Use 36-gauge (maximum) K-type thermocouples.
Ethernet Controller I210 —Thermal Considerations 13.8 PCB Layout Guidelines The following general PCB design guidelines are recommended to maximize the thermal performance of QFN packages: • When connecting ground (thermal) vias to the ground planes, do not use thermal-relief patterns. • Thermal-relief patterns are designed to limit heat transfer between the vias and the copper planes, thus constricting the heat flow path from the component to the ground planes in the PCB.
Diagnostics—Ethernet Controller I210 14.0 Diagnostics 14.1 Customer Visible Features 14.1.1 JTAG Test Mode Description The I210 includes a JTAG (TAP) port that is compliant with the IEEE standard 1149.1, 2001 Edition (JTAG). Institute of Electrical and Electronics Engineers (IEEE). The TAP controller is accessed serially through the four dedicated pins TCK, TMS, TDI, and TDO. TMS, TDI, and TDO operate synchronously with TCK which is independent of all other clock within the I210.
Ethernet Controller I210 —Diagnostics Table 14-2. TAP Instructions Supported Instruction Description Comment BYPASS The BYPASS command selects the Bypass Register, a single bit register connected between TDI and TDO pins. This allows more rapid movement of test data to and from other components in the system. IEEE 1149.1 Std. Instruction EXTEST The EXTEST Instruction allows circuitry or wiring external to the devices to be tested.
Packet Types—Ethernet Controller I210 Appendix A. Packet Types This section describes the packet types supported by the header split/replication and other features. A.1 Packet Types for Header Split/Replication The following packet types describe the different formats of the packets that are supported by the packet split or replicate feature in the I210. It describes the packets in the split-header point of view.
Ethernet Controller I210 —Packet Types A.1.3 Type 1 Ethernet (VLAN/SNAP) IP Packets A.1.3.1 Type 1.1 Ethernet, IP, Data This packet type contains only Ethernet and IPv4 headers while the payload header of the IP is not IPv6/TCP/UDP. The header of this type of packet is split/replicated only if PSRTYPE.PSR_TYPE1 is set.
Packet Types—Ethernet Controller I210 A.1.3.2 Type 1.2: Ethernet (VLAN/snap), IPv4, TCP This packet type contains all three Ethernet, IPv4, and TCP headers. The header of this type of packet is split/replicated only if PSRTYPE.
Ethernet Controller I210 —Packet Types N = (IP HDR length –5) * 4. F = (TCP header length – 5) * 4. A.1.3.3 Type 1.3: Ethernet (SNAP/VLAN), IPv4, UDP This packet type contains all three Ethernet, IPv4, and UDP headers. The header of this type of packet is split/replicated only if PSRTYPE.PSR_TYPE3 is set.
Packet Types—Ethernet Controller I210 A.1.3.4 Type 1.4: Ethernet, IPv4, IPv6 A.1.3.4.
Ethernet Controller I210 —Packet Types Offset # of Bytes Field Value Action 18+D+S 2 Identification - Ignore 20+D+S 2 Fragment Info 0x00 Compare 22+D+S 1 Time to live - Ignore 23+D+S 1 Protocol 0x29 Compare 24+D+S 2 Header Checksum - Ignore 26+D+S 4 Source IP Address - Ignore 30+D+S 4 Destination IP Address - Ignore 34+D+S N Possible IP Options Comment Ipv6 Ignore Ipv6 Header 34+D+S+N 1 Version/ Traffic Class 0x6X Compare 35+D+S+N 3 Traffic Class/Flow La
Packet Types—Ethernet Controller I210 Offset # of Bytes Field Value Action 14+D+S 1 Version/ HDR length 0x4X Compare 15+D+S 1 Type of Service - Ignore 16+D+S 2 Packet Length - Ignore 18+D+S 2 Identification - Ignore 20+D+S 2 Fragment Info 0x00 Compare 22+D+S 1 Time to live - Ignore 23+D+S 1 Protocol 0x29 Compare 24+D+S 2 Header Checksum - Ignore 26+D+S 4 Source IP Address - Ignore 30+D+S 4 Destination IP Address - Ignore 34+D+S N Possible IP Options
Ethernet Controller I210 —Packet Types T = D+S+N+B N = (IP HDR length – 5) * 4. F = (TCP HDR length – 5)*4 A.1.3.4.6 Type 1.4.3: Ethernet (VLAN/SNAP), IPv4, IPv6, UDP This packet type contains all four Ethernet, IPv4, IPv6, and UDP headers. The header of this type of packet is split/replicated only if PSRTYPE.PSR_TYPE6 is set.
Packet Types—Ethernet Controller I210 Offset # of Bytes Field Value Action Comment UDP Header 74+D+S+N+B 2 Source Port Not (0x801) Check Not NFS packet 76+D+S+N+B 2 Destination Port Not (0x801) Check Not NFS packet 78+D+S+N+B 2 Length - Ignore 80+D+S+N+B 2 Checksum - Ignore In this case the packet is split after (82+D+S+N+B) bytes. N = (IP HDR length – 5) * 4. A.1.4 Type 2: Ethernet, IPv6 A.1.4.1 Type 2.
Ethernet Controller I210 —Packet Types The last next header field of the IP section field should not be 0x11/0x06 (TCP/UDP). A.1.4.2 Type 2.2: Ethernet (VLAN/SNAP) IPv6 TCP This packet type contains all three Ethernet, IPv6, and TCP headers. The header of this type of packet is split/replicated only if PSRTYPE.PSR_TYPE8 is set.
Packet Types—Ethernet Controller I210 In this case the packet is split after (54+D+S+N+F) bytes. F = (TCP header length – 5) * 4 The last Next-header field of the last header of the IP section must be 0x11. A.1.4.3 Type 2.3: Ethernet (VLAN/SNAP) IPv6 UDP This packet type contains all three Ethernet, IPv6, and UDP headers. The header of this type of packet is split/replicated only if PSRTYPE.PSR_TYPE9 is set.
Ethernet Controller I210 —Packet Types A.1.5 Type 3: NFS Packets NFS headers can come in all the frames that contain a UDP/TCP header. The NFS (and RPC headers) are extensions to these types of packets. All of the packets previously described in sections A.1.3.2, A.1.3.2, A.1.3.4.5, A.1.3.4.5, A.1.4.3, and A.1.4.2, can accommodate NFS headers. PSRTYPE.PSR_TYPE11/12/14/15/18/19 controls the split/replication behavior of NFS packets. See Section 8.10.3 for details.
Packet Types—Ethernet Controller I210 A.1.5.1.1 Type 3.1.
Ethernet Controller I210 —Packet Types A.1.5.1.2 Type 3.1.
Packet Types—Ethernet Controller I210 A.1.5.1.3 Type 3.1.
Ethernet Controller I210 —Packet Types A.1.5.2 Type 3.2: NFS Read Response A.1.5.2.1 The I210 should be configured to the right version via its configuration space. A.1.5.2.2 Type 3.2.
Packet Types—Ethernet Controller I210 A.1.5.2.3 Type 3.2.
Ethernet Controller I210 —Packet Types A.1.5.2.4 Type 3.2.
Packet Types—Ethernet Controller I210 Table A-1. IPv4 Header (Traditional Representation) Source Address Destination Address Options Table A-2.
Ethernet Controller I210 —Packet Types Table A-4. IPv6 Header (Little Endian Order) Byte3 7 6 5 4 3 Byte2 2 1 0 7 6 5 4 Byte1 3 2 1 0 7 6 5 4 3 Byte0 2 1 0 7 6 Flow Label Hop Limit 5 4 3 2 Version Next Header Type 1 0 Priority Payload Length LSB MSB Source Address Destination Address Extensions A TCP or UDP frame uses a 16 bit wide one's complement checksum. The checksum word is computed on the outgoing TCP or UDP header and payload, and on the pseudo header.
Packet Types—Ethernet Controller I210 The TCP header is always a multiple of 32-bit words. TCP options might occupy space at the end of the TCP header and are a multiple of 8 bits in length. All options are included in the checksum. The checksum also covers a 96-bit pseudo header conceptually prefixed to the TCP Header (see Table A-7). For IPv4 packets, this pseudo header contains the IP Source Address, the IP Destination Address, the IP Protocol field, and TCP Length.
Ethernet Controller I210 —Packet Types • The Upper-Layer Packet Length in the pseudo-header is the length of the upper-layer header and data (e.g., TCP header plus TCP data). Some upper-layer protocols carry their own length information (e.g., the Length field in the UDP header); for such protocols, that is the length used in the pseudo- header.
Packet Types—Ethernet Controller I210 Table A-11. UDP Header (Little Endian Order) Byte3 0 1 2 3 Byte2 4 5 6 7 0 1 2 3 Byte1 4 5 6 7 0 1 2 3 4 Byte0 5 6 7 0 1 Destination Port Source Port Checksum Length 2 3 4 5 6 7 UDP pseudo header has the same format as the TCP pseudo header.
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