Intel DMA Coalescing White Paper

For more information on Intel® PMTs and the Intel® I350A, visit wwwintelcom/go/ethernet
C-state entry by the OS is on a per-core
basis. These are called “Core C States”
(or CC3, for example, for Core C3). When
all CPU cores simultaneously go into the
same or deeper C state, the supervisory
rmware controlling the package
(previously called “socket”) can enable the
entire package to transition to a Package
C state. The dramatic power savings occur
whenever the entire package enters
these Package C3 or Package C6 states.
However, I/O activity, even at seemingly
platform idle, such as graphics DMA, disk
DMA, or LAN DMA, prevents the package
from entry into these deep power states.
As such, much of the time spent on
platform tuning is used to identify the
source of this activity. An example of
this is running a copy of Windows that
hasn’t been activated; Windows causes
a small amount of disk activity that isn’t
noticeable by looking at CPU usage alone.
To determine the current Package C-state
residency, special software must be used.
On Linux, the powertop* tool versions 2.0
and later support reporting these metrics,
as do the Linux “turbostat” tool. For
Windows, there are Intel tools: the Intel
Battery Life Analyzer tool (BLA) reports
the Package C states (as well as the actual
cause of the I/O activity in many cases) on
Intel client platforms. On server platforms,
a special perfmon DLL must be installed to
read the processor-specic performance
counters.
Ideally, on a well-tuned platform at idle,
the platform should see 85% or greater
Package C6 % residency. At this point,
various networking benchmarks can be
stated to evaluate the benets of DMA
coalescing and other Intel PMT features.
References
Designing Power-Friendly Devices (Intel
Whitepaper)
Energy-Efcient Platforms/Green Hill
Software (Intel Whitepaper)
Intel® I350 Quad-/Dual-Port GbE LAN
Controller Datasheet
Figure 6
Intel® I350 Ethernet Controller & DMA Coalescing
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